AD9640SLASHPCB datasheet(17/41 Pages) AD

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Preliminary Technical Data

AD9640

Rev. PrD | Page 17 of 41

THEORY OF OPERATION

The AD9640 dual ADC design may be used for diversity

reception of signals, where the ADCs are operating identically

on the same carrier but from two separate antennae. The ADCs

can also be operated with independent analog inputs. The user

can sample any fs/2 frequency segment from dc to 100 MHz

using appropriate low-pass or band-pass filtering at the ADC

inputs with little loss in ADC performance. Operation to 200

MHz analog input is permitted, but at the expense of increased

ADC distortion.

In non-diversity applications, the AD9640 can be used as a

baseband receiver where one ADC is used for I input data and

the other used for Q input data.

Synchronizaton capability is provided to allow synchronized

timing between multiple channels or multiple devices.

Programming and control of the AD9640 is accomplished using

a 3-bit SPI compatible serial interface.

ADC ARCHITECTURE

The AD9640 architecture consists of a dual front-end sample

and hold amplifier (SHA) followed by a pipelined switched

capacitor ADC. The quantized outputs from each stage are

combined into a final 14-bit result in the digital correction

logic. The pipelined architecture permits the first stage to

operate on a new input sample, while the remaining stages

operate on preceding samples. Sampling occurs on the rising

edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The input stage of each channel contains a differential SHA that

can be ac- or dc-coupled in differential or single-ended modes.

The output-staging block aligns the data, carries out the error

correction, and passes the data to the output buffers. The output

buffers are powered from a separate supply, allowing

adjustment of the output voltage swing. During power-down,

the output buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9640 is a differential switched

capacitor SHA that has been designed for optimum

performance while processing a differential input signal.

The clock signal alternatively switches the SHA between sample

mode and hold mode (see x). When the SHA is switched into

sample mode, the signal source must be capable of charging the

sample capacitors and settling within one-half of a clock cycle.

A small resistor in series with each input can help reduce the

peak transient current required from the output stage of the

driving source. A shunt capacitor can be placed across the

inputs to provide dynamic charging currents. This passive

network creates a low-pass filter at the ADC’s input; therefore,

the precise values are dependant upon the application.

In IF undersampling applications, any shunt capacitors should

be reduced. In combination with the driving source impedance,

they would limit the input bandwidth. See the application notes

AN-742 and AN-827, and the Analog Dialogue article

“Transformer-Coupled Front-End for Wideband A/D Converters”

for more information on this subject. In general, the precise

values are dependent on the application.

Figure21. Switched-Capacitor SHA Input

For best dynamic performance, the source impedances driving

VIN+ and VIN– should be matched.

An internal differential reference buffer creates positive and

negative reference voltages that define the input span of the

ADC core. The span of the ADC core is set by the buffer to be

2X VREF.

Input Common Mode

The analog inputs of the AD9640 are not internally dc-biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that VCM = 0.5 × AVDD is

recommended for optimum performance, but the device

functions over a wider range with reasonable performance (see

Figure x). An on-board common-mode voltage reference is

included in the design and is available from the CML pin.

Optimum performance is achieved when the common-mode

voltage of the analog input is set by the CML pin voltage

(typically 0.55 × AVDD).

Differential Input Configurations

Optimum performance is achieved while driving the AD9640

in a differential input configuration. For baseband applications,

the AD8138 differential driver provides excellent performance

and a flexible interface to the ADC. The output common-mode

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