AD9640SLASHPCB datasheet(29/41 Pages) AD

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Preliminary Technical Data

AD9640

Rev. PrD | Page 29 of 41

DC CORRECTION

Since the DC offset of the ADC can be significantly larger than

the signal we are trying to measure a simple DC correction

circuit is included to null the DC offset before measuring the

power. The DC Correction circuit can also be switched into the

main signal path but this may not be appropriate if the ADC is

digitizing a time-varying signal with significant DC content

such as GSM.

DC Correction Bandwidth

The DC correction circuit is basically a HP filter with a

programmable BW ranging between 0.15Hz and 1.2kHz. The

BW is controlled by writing the 4-bit DC correction register

located in bits 5:2 at address 0x10C. Table xx shows the BW

values for each of the 16 possible programmed values.

Table xx. DC Correction Bandwidth Settings

DC Correction Factor

reg.10C<5:2>

Bandwidth (Hz)

0000

1218.56

0001

609.28

0010

304.64

0011

152.32

0100

76.16

0101

38.08

0110

19.04

0111

9.52

1000

4.76

1001

2.38

1010

1.19

1011

0.60

1100

0.30

1101

0.15

1110

0.15

1111

0.15

DC Correction Readback

The current DC correction value can be read back in registers

0x10D and 0x10E for channel A and registers 0x10F and 0x110

for channel B. The DC correction value is a 14 bit value that

can span the entire input range of the ADC.

DC Correction Freeze

Setting the DC Correction Freeze bits freezes the DC correction

at its current state and continues to use the last updated value as

the DC correction value. Clearing this bit restarts the DC

correction and adds the currently calculated value to the data.

DC Correction Enable Bits

Setting bit 0 of register 0x10C enables the DC correction for use

in the Signal monitor calculations. The calculated DC

correction value can be added to the output data signal path by

setting bit 1 of register 0x10C.

SIGNAL MONITOR SPORT OUTPUT

The SPORT is a serial interface with three output pins, the SMI

SCLK (SPORT clock), SMI_SDFS (SPORT frame sync) and

SMI_SDO (SPORT data). The SPORT is the master, and drives

all three pins out of the chip.

SMI SCLK

The data and frame sync are driven on the positive edge of the

SMI SCLK. The SMI SCLK has three possible baud rates. They

are ½, ¼, or 1/8 the ADC clock rate, based on the SPORT

controls. The SMI SCLK can also be gated off when not sending

any data, based on the SMI SCLK sleep bit. Gating off the SMI

SCLK when it is not needed will reduce the coupling errors

back into the signal path if these prove to be a problem in the

system. This has the disadvantage of spreading the frequency

content of the clock so this can be left running to ease

frequency planning if desired.

SMI SDFS

The SMI_SDFS is the Serial Data Frame Sync, and defines the

start of a frame. One SPORT frame includes data from both

datapaths. The data from Datapath A is sent just after the frame

sync, followed by data from Datapath B.

SMI SDO

The SMI_SDO is the serial data out of the block. The data is

sent MSB first on the next positive edge after the SMI_SDFS.

Each data output block includes one or more of RMS

magnitude, Peak level, and Threshold Crossing values from

both datapaths in the stated order. If enabled the data is sent

RMS first, followed by Peak, and Threshold as shown in Figure

Figure 26. Signal monitor SPORT Output Timing (RMS, Peak, and Threshold

Enabled)

Figure 27. Signal monitor SPORT Output Timing (RMS and Threshold

Enabled)

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