AD9640SLASHPCB datasheet(27/41 Pages) AD

27 / 41 page

Preliminary Technical Data

AD9640

Rev. PrD | Page 27 of 41

SIGNAL MONITOR

The Signal monitoring block serves to characterize the signal

being digitized by the ADC. It operates in one to three modes

to compute the RMS Input Magnitude, Peak Magnitude, and/or

the number of samples that the Magnitude crosses a particular

threshold. Together these functions can be used to gain insight

into the signal characteristics and can be used to estimate the

Peak/Average ratio or even the shape of the CCDF curve (peak

to average ratio) of the input signal. This information can be

used to drive an AGC loop and to optimize the range of the

ADC in the presence of real world signals.

The signal monitor result values can be obtained from the part

by either reading back internal registers at addresses 0x116 to

0x11B using the SPI port or by using the signal monitor SPORT

output. The output contents of the SPI accessible signal monitor

registers is set via the 2 power-monitor mode bits of the signal

monitor control register. Both ADC channels must be

configured for the same signal monitor mode. Separate SPI

accessible 20 bit Signal monitor Value (PMV) output registers

are provided for each ADC channel. Any combination of the

signal monitor functions can also be output to the user via a

serial SPORT interface. These outputs are enabled using the

Peak Power Output Enable, RMS Magnitude Output Enable,

and Threshold Crossing Output Enable bits in the Signal

monitor SPORT Control Register.

For each of the signal monitor measurements a programmable

Signal Monitor Period Register (SMPR) controls the duration

of the measurement. This time period is programmed as the

number of input clock cycles in a 24-bit ADC monitor period

16.78 (2^24) million samples.

Since the DC offset of the ADC can be significantly larger than

the signal of interest a simple DC correction circuit is included

as part of the signal monitor block to null the DC offset before

measuring the power.

PEAK DETECTOR MODE (MODE BITS 01)

The magnitude of the input port signal is monitored over a

programmable time period (given by SMPR) to give the peak

value detected. This function is enabled by programming a logic

1 in the power-monitor mode bits of the power-monitor control

Signal monitor SPORT Control Register. The 24-bit SMPR must

be programmed before activating this mode.

After enabling this mode, the value in the SMPR is loaded into a

monitor period timer and the countdown is started. The

magnitude of the input signal is compared to the internal peak

level holding register, and the greater of the two is updated back

into the peak level holding register. The initial value of the peak

level holding register is set to the current ADC input signal

magnitude. This comparison continues until the monitor

period timer reaches a count of 1.

When the monitor period timer reaches a count of 1, the 13 bit

value in the peak level holding register is transferred to a

holding register, which can be read through the SPI port or

output through the SPORT serial interface. The monitor period

timer is reloaded with the value in the SMPR, and the

countdown is started. Also, the first input sample’s magnitude is

updated in the peak level holding register, and the comparison

and update procedure, as explained above, continues.

Figure 23 is a block diagram of the peak detector logic. The

PMV contains the absolute magnitude of the peak detected by

the peak detector logic.

POWER MONITOR

HOLDING

MAGNITUDE

STORAGE

COMPARE

A>B

MEMORY

MAP

FROM

MEMORY

MAP

FROM

INPUT

PORTS

LOAD

CLEAR

LOAD

IS COUNT = 1?

DOWN

COUNTER

INTERRUPT

CONTROLLER

POWER MONITOR

PERIOD REGISTER

Figure 23. ADC Input Peak Detector Block Diagram

RMS/MS MAGNITUDE MODE (MODE BITS 00)

In this mode, the RMS or MS magnitude of the input port

signal is integrated (by adding an accumulator) over a

programmable time period (given by SMPR) to give the RMS or

MS magnitude of the input signal. This mode is set by

programming Logic 0 in the signal monitor mode bits of the

signal monitor control register or by setting the RMS

Magnitude Output Enable bit in the Signal monitor SPORT

Control Register. The 24-bit SMPR, representing the period

over which integration is performed, must be programmed

before activating this mode.

After enabling this mode, the value in the SMPR is loaded into a

monitor period timer, and the countdown is started

immediately. Each input sample is converted to floating point

format and squared. It is then converted to 11 bit fixed point

format and is added to the contents of a 24-bit holding register,

thus performing an accumulation. The integration continues

until the monitor period timer reaches a count of 1.

When the monitor period timer reaches a count of 1, the square

root of the value in the holding register is taken and transferred

to the power-monitor holding register (after some formatting),

which can be read through the SPI port or output through the

AD9640/PCB Datenblatt(PDF) 27 Page - Analog Devices

AD9640/PCB Datenblatt(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datenblatt Download

Link URL