AD9640SLASHPCB datasheet(25/41 Pages) AD

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Preliminary Technical Data

AD9640

Rev. PrD | Page 25 of 41

ADC OVERRANGE (OVR)

The ADC Overrange bit becomes active when an overrange is

detected on the input of the ADC. The overrange condition is

determined at the output of the ADC pipline and is therefore

subject to the TBD ADC clock cycle latency. So an overrange at

the input would be indicated by this bit TBD clock cycles after it

occurred.

GAIN SWITCHING

The AD9640 includes circuitry that is useful in applications

where either large dynamic ranges exist or where gain ranging

converters are employed. This circuitry allows digital thresholds

to be set such that an upper and a lower threshold can be

programmed. Fast detect modes 2 through 7 support various

combinations of the gain switching options.

One such use of this may be to detect when an ADC is about to

reach full scale with a particular input condition. The results

would be to provide a flag that could be used to quickly insert

an attenuator that would prevent ADC overdrive.

Coarse Upper Threshold (C_UT)

The coarse upper threshold bit is asserted if the input level

present on the ADC Fast Magnitude bits is greater than the level

programmed in the coarse upper threshold register at address

0x105 bits [2:0]. This value is compared with the ADC Fast

Magnitude Bits [2:0]. The coarse upper threshold levels are

shown in Table x.x. This bit remains asserted for a minimum of

2 ADC clock cycles or until the signal drops below the

threshold level.

Table xx. Fast Magnitude Nominal Threshold Levels

Coarse Upper

Threshold Register

[2:0]

C_UT active when

signal magnitude

in dB below FS is

greater than

000

001

TBD

010

TBD

011

TBD

100

TBD

101

TBD

110

TBD

111

TBD

Fine Upper Threshold (F_UT)

The Fine Upper Threshold bit will be asserted if the input

magnitude exceeds the value programmed in the Fine Upper

Threshold Register located at addresses 0x106 and 0x107. This

is a 13 bit threshold register that is compared with the

magnitude at the output of the ADC. This comparison is

subject to the ADC clock latency but allows a finer, more

accurate comparison. The fine threshold magnitude is defined

by equation x.x.

dBFS = 20 log (threshold mag/2^13)

Fine Lower Threshold (F_LT)

The Fine Lower Threshold bit will be asserted if the input

magnitude is less than value programmed in the Fine Lower

Threshold Register located at addresses 0x108 and 0x109. The

fine lower threshold register is a 13 bit register that is compared

with the magnitude at the output of the ADC. This comparison

is delayed by the ADC clock latency but provides an accurate

comparison. The fine threshold magnitude is defined by

equation x.x.

dBFS = 20 log (threshold mag/2^13)

Increment Gain (IG) and Decrement Gain (DG)

The Increment Gain and decrement gain outputs are intended

to be used together to provide information to enable external

gain control. The Decrement Gain output works identically to

the Coarse Upper Threshold output. This bit is asserted when

the input magnitude is greater than the three bit value in the

Coarse Upper Threshold Register. The Increment Gain output

is similar to the Fine Lower Threshold bit except that it will be

asserted only if the input magnitude is less than value

programmed in the Fine Lower Threshold Register for greater

than the 16 bit Dwell Time value located at addresses 0x10A

and 0x10B. The dwell time is set in units of ADC input clock

cycles ranging from 1 to 65535. The fine lower threshold

at the output of the ADC. This comparison is subject to the

ADC clock latency but allows a finer, more accurate

comparison. The fine threshold magnitude is defined by

equation x.x.

The decrement gain output works off the ADC fast detect bits

providing a fast indication of potential overrange conditions.

The increment gain uses the comparison at the output of the

ADC requiring the input magnitude to remain below an

accurate programmable level for a predefined period before

signaling external circuitry to increase the gain.

The operation of the increment gain and decrement gain bits is

shown in Figure x.x.

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