AD9640SLASHPCB datasheet(11/41 Pages) AD

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Preliminary Technical Data

AD9640

Rev. PrD | Page 11 of 41

Pin No.

Mnemonic

Type

Function

ADC INPUTS

VIN+A

Input

Differential Analog Input Pin (+) for Channel A.

VIN-A

Input

Differential Analog Input Pin (−) for Channel A.

VIN+B

Input

Differential Analog Input Pin (+) for Channel B.

VIN−B

Input

Differential Analog Input Pin (−) for Channel B.

VREF

I/O

Voltage Reference Input/Output.

SENSE

Input

Voltage Reference Mode Select (See Table x for details)

RBIAS

Input

External Reference Bias Resistor

CML

Output

Common Mode Level Bias Output for Analog Inputs

CLK+

Input

ADC Master Clock – True (ADC Clock can be driven using single ended CMOS – See

Figure x.x for recommended connection)

CLK-

Input

ADC Master Clock - Complement (ADC Clock can be driven using single ended

CMOS – See Figure x.x for recommended connection)

ADC Fast Detect Outputs

FD0A

Output

Channel A Fast Detect Indicator (See Table x for full detials)

FD1A

Output

Channel A Fast Detect Indicator (See Table x for full detials)

FD2A

Output

Channel A Fast Detect Indicator (See Table x for full detials)

FD3A

Output

Channel A Fast Detect Indicator (See Table x for full detials)

FD0B

Output

Channel B Fast Detect Indicator (See Table x for full detials)

FD1B

Output

Channel B Fast Detect Indicator (See Table x for full detials)

FD2B

Output

Channel B Fast Detect Indicator (See Table x for full detials)

FD3B

Output

Channel B Fast Detect Indicator (See Table x for full detials)

Digital INPUTS

SYNC

Input

Digital Synchronization Pin(Slave Mode Only)

Digital OUTPUTS

12, 13, 14,

15, 16, 17,

18, 19, 22,

23, 25, 26,

27, 28

D0A-D13A

Output

Channel A CMOS output data

58, 59, 60,

61, 62, 63,

2, 3, 4, 5, 6,

7, 8, 9

D0B-D13B

Output

Channel B CMOS output data

DCOA

Output

Channel A Data Clock Output

DCOB

Output

Channel B Data Clock Output

SPI CONTROL

SCLK/DFS

Input

SPI Serial Clock/Data Format Select Pin in External Pin Mode

SDIO/DCS

I/O

SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode

CSB

Input

SPI Chip Select (Active Low)

Serial Port

SMI SDO/OEB

I/O

Signal monitor Serial Data Output/Output Enable Input (Active Low) in External Pin

Mode

SMI SDFS

Output

Signal monitor Serial Data Frame Sync

SMI SCLK/PDWN

I/O

Signal monitor Serial Clock Output/Power Down Input in External Pin Mode

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