WM8994ECSSLASHR datasheet(48/363 Pages) CIRRUS

48 / 363 page

WM8994

Rev 4.6

INPUT PGA ENABLE

The Input PGAs are enabled using register bits IN1L_ENA, IN2L_ENA, IN1R_ENA and IN2R_ENA,

as described in Table 2. The Input PGAs must be enabled for microphone input on the respective

input pins, or for line input on the inverting input pins IN1LN, IN1RN, IN2LN, IN2RN.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (0002h)

Power

Management

(2)

IN2L_ENA

IN2L Input PGA Enable

0 = Disabled

1 = Enabled

IN1L_ENA

IN1L Input PGA Enable

0 = Disabled

1 = Enabled

IN2R_ENA

IN2R Input PGA Enable

0 = Disabled

1 = Enabled

IN1R_ENA

IN1R Input PGA Enable

0 = Disabled

1 = Enabled

Table 2 Input PGA Enable

For normal operation of the input PGAs, the reference voltage VMID and the bias current must also be

enabled. See “Reference Voltages and Master Bias” for details of the associated controls VMID_SEL

and BIAS_ENA.

INPUT PGA CONFIGURATION

Each of the Input PGAs can operate in a single-ended or differential mode. In differential mode, both

inputs to the PGA are connected to the input source. In single-ended mode, the non-inverting input to

the PGA must be connected to VMID. Configuration of the PGA inputs to the WM8994 input pins is

controlled using the register bits shown in Table 3.

Single-ended microphone operation is configured by connecting the input source to the inverting input

of the applicable PGA. The non-inverting input of the PGA must be connected to the buffered VMID

reference. Note that the buffered VMID reference must be enabled, using the VMID_BUF_ENA

Differential microphone operation is configured by connecting the input source to both inputs of the

applicable PGA.

Line inputs to the input pins IN1LN, IN2LN, IN1RN and IN2RN must be connected to the applicable

PGA. The non-inverting input of the PGA must be connected to VMID.

Line inputs to the input pins IN1LP, IN2LP, IN1RP or IN2RP do not connect to the input PGAs. The

non-inverting inputs of the associated PGAs must be connected to VMID. The inverting inputs of the

associated PGAs may be used as separate mic/line inputs if required.

The maximum available attenuation on any of these input paths is achieved by using register bits

shown in Table 3 to disconnect the input pins from the applicable PGA.

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