 |
Datenblatt-Suchmaschine für elektronische Bauteile |
|
|
Datenblatt-Suchmaschine für elektronische Bauteile |
|
WM8994ECS/R Datenblatt(PDF) 37 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
WM8994ECS/R Datenblatt(HTML) 37 Page - Cirrus Logic |
|
|
37 / 363 page  WM8994 Rev 4.6 37 DIGITAL AUDIO INTERFACE - SLAVE MODE BCLK (input) LRCLK (input) ADCDAT (output) DACDAT (input) tDS tDD tDH tLRH tLRSU tBCH tBCL tBCY VIH VIL VIH VIL VOH VOL VIH VIL Figure 5 Audio Interface Timing - Slave Mode Note that BCLK and LRCLK inputs can be inverted if required; Figure 5 shows the default, non- inverted polarity. Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Slave Mode BCLK cycle time tBCY 160 ns BCLK pulse width high tBCH 64 ns BCLK pulse width low tBCL 64 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 48 ns DACDAT set-up time to BCLK rising edge tDS 32 ns Note that the descriptions above assume non-inverted polarity of BCLK and LRCLK. |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
German ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
