WM8994ECSSLASHR datasheet(61/363 Pages) CIRRUS

61 / 363 page

WM8994

Rev 4.6

ADC CLOCKING CONTROL

Clocking for the ADCs is derived from SYSCLK. The required clock is enabled when the

SYSDSPCLK_ENA register is set.

The ADC clock rate is configured automatically, according to the AIFn_SR, AIFnCLK_RATE and

ADC_OSR128 registers. (See “Clocking and Sample Rates” for further details of the system clocks

and control registers.)

When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the ADC clocking is

controlled by the AIF1_SR and AIF1CLK_RATE registers.

When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then the ADC clocking is

controlled by the AIF2_SR and AIF2CLK_RATE registers.

The supported ADC clocking configurations are described in Table 14 (for ADC_OSR128=1) and

Table 15 (for ADC_OSR128=0). The ADC_OSR128 bit is set by default, giving best audio

performance.

SAMPLE

RATE (kHz)

SYSCLK RATE (AIFnCLK / fs ratio)

128

192

256

384

512

768

1024

1536



11.025



22.05



44.1



88.2

When ADC_OSR128=1, ADC operation is only supported for the configurations indicated above

Table 14 ADC Clocking - ADC_OSR128 = 1 (Default)

SAMPLE

RATE (kHz)

SYSCLK RATE (AIFnCLK / fs ratio)

128

192

256

384

512

768

1024

1536



11.025



22.05



44.1



88.2

When ADC_OSR128=0, ADC operation is only supported for the configurations indicated above

Table 15 ADC Clocking - ADC_OSR128 = 0

The clocking requirements in Table 14 and Table 15 are only applicable to the AIFnCLK that is

selected as the SYSCLK source. Note that both clocks (AIF1CLK and AIF2CLK) must satisfy the

requirements noted in the “Clocking and Sample Rates” section.

The applicable clocks (SYSCLK, and AIF1CLK or AIF2CLK) must be present and enabled when using

the Analogue to Digital Converters (ADCs).

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