WM8994ECSSLASHR datasheet(53/363 Pages) CIRRUS

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WM8994

Rev 4.6

INPUT MIXER ENABLE

The WM8994 has two analogue input mixers which allow the Input PGAs and Line Inputs to be

combined in a number of ways and output to the ADCs, Output Mixers, or directly to the output drivers

via bypass paths.

The input mixers MIXINL and MIXINR are enabled by the MIXINL_ENA and MIXINR_ENA register

bits, as described in Table 6. These control bits also enable the RXVOICE input path, described in the

following section.

For normal operation of the input mixers, the reference voltage VMID and the bias current must also

be enabled. See “Reference Voltages and Master Bias” for details of the associated controls

VMID_SEL and BIAS_ENA.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (0002h)

Power

Management

(2)

MIXINL_ENA

Left Input Mixer Enable

(Enables MIXINL and RXVOICE input to

MIXINL)

0 = Disabled

1 = Enabled

MIXINR_ENA

Right Input Mixer Enable

(Enables MIXINR and RXVOICE input to

MIXINR)

0 = Disabled

1 = Enabled

Table 6 Input Mixer Enable

INPUT MIXER CONFIGURATION AND VOLUME CONTROL

The left and right channel input mixers MIXINL and MIXINR can be configured to take input from up to

five sources:

IN1L or IN1R Input PGA

IN2L or IN2R Input PGA

IN1LP or IN1RP pin (PGA bypass)

RXVOICE mono differential input from IN2LP/VRXN and IN2RP/VRXP

MIXOUTL or MIXOUTR Output Mixer (Record path)

The Input Mixer configuration and volume controls are described in Table 7 for the Left input mixer

(MIXINL) and Table 8 for the Right input mixer (MIXINR). The signal levels from the Input PGAs may

be set to Mute, 0dB or 30dB boost. Gain controls for the PGA bypass, RXVOICE and Record paths

provide adjustment from -12dB to +6dB in 3dB steps.

When using the IN1LP or IN1RP signal paths direct to the input mixers (PGA bypass paths), a signal

gain of +15dB can be selected using the IN1RP_MIXINR_BOOST or IN1LP_MIXINL_BOOST register

bits. See Table 7 and Table 8 for further details.

When using the IN1LP or IN1RP signal paths direct to the input mixers (PGA bypass paths), the

buffered VMID reference must be enabled, using the VMID_BUF_ENA register, as described in

“Reference Voltages and Master Bias”.

To prevent pop noise, it is recommended that gain and mute controls for the input mixers are not

modified while the signal paths are active. If volume control is required on these signal paths, it is

recommended that this is implemented using the input PGA volume controls or the ADC volume

controls.

The ADC volume controls are described in the “Analogue to Digital Converter (ADC)”

section.

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