WM8994ECSSLASHR datasheet(57/363 Pages) CIRRUS

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WM8994

Rev 4.6

DIGITAL MICROPHONE INTERFACE

The WM8994 supports a four-channel digital microphone interface. Two channels of audio data are

multiplexed on the DMICDAT1 pin and a further two channels are multiplexed on the DMICDAT2 pin.

All four channels are clocked using the DMICCLK output pin.

The DMICDAT1 function is shared with the IN2LN pin; the analogue signal paths from IN2LN cannot

be used when this pin is used for DMICDAT1 digital microphone input.

The DMICDAT2 function is shared with the IN2RN pin; the analogue signal paths from IN2RN cannot

be used when this pin is used for DMICDAT2 digital microphone input.

The digital microphone interface is referenced to the MICBIAS1 voltage domain; the MICBIAS1 output

must be enabled (MICB1_ENA = 1) when using the digital microphone interface.

The MICBIAS1 generator is suitable for use as a low noise supply for the digital microphones. (See

“Analogue Input Signal Path” for details of the MICBIAS1 generator.)

When digital microphone input is enabled, the WM8994 outputs a clock signal on the DMICCLK pin.

The DMICCLK frequency for all supported digital microphone clocking modes is described later in this

section.

A pair of digital microphones is connected as illustrated in Figure 19. The microphones must be

configured to ensure that the Left mic transmits a data bit when DMICCLK is high, and the Right mic

transmits a data bit when DMICCLK is low. The WM8994 samples the digital microphone data at the

end of each DMICCLK phase. Each microphone must tri-state its data output when the other

microphone is transmitting.

Digital Mic

DMICDAT1

4.7uF

MICBIAS1

AGND

Digital Mic

DMICCLK

VDD

CLK

DATA

VDD

CLK

DATA

CHAN

VDD

Digital

Microphone

Interface

Figure 19 Digital Microphone Input

The DMICDAT1 digital microphone channels are enabled using DMIC1L_ENA and DMIC1R_ENA.

When these signal paths are enabled, the respective ADC path is disconnected and the digital

microphone data is routed to the digital mixing input bus, as illustrated in “Digital Mixing”.

The DMICDAT2 digital microphone channels are enabled using DMIC2L_ENA and DMIC2R_ENA.

When these signal paths are enabled, the digital microphone data is routed to the digital mixing input

bus, as illustrated in “Digital Mixing”.

Two microphone channels are interleaved on DMICDAT1; another two channels are interleaved on

DMICDAT2. The timing is illustrated in Figure 20. Each microphone must tri-state its data output when

the other microphone is transmitting.

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