WM8994ECSSLASHR datasheet(73/363 Pages) CIRRUS

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WM8994

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1344 (0540h)

AIF2 DRC (1)

AIF2DAC_DRC_

ENA

Enable DRC in AIF2DAC playback

path

0 = Disabled

1 = Enabled

AIF2ADCL_DRC

_ENA

Enable DRC in AIF2ADC (Left)

record path

0 = Disabled

1 = Enabled

AIF2ADCR_DRC

_ENA

Enable DRC in AIF2ADC (Right)

record path

0 = Disabled

1 = Enabled

Table 22 DRC Enable

The following description of the DRC is applicable to all three DRCs. The associated register control

fields are described in Table 24, Table 25 and Table 26 for the respective DRCs.

Note that, where the following description refers to register names, the generic prefix [DRC] is quoted:



For the DRC associated with AIF1 timeslot 0, [DRC] = AIF1DRC1.



For the DRC associated with AIF1 timeslot 1, [DRC] = AIF1DRC2.



For the DRC associated with AIF2, [DRC] = AIF2DRC.

DRC COMPRESSION / EXPANSION / LIMITING

The DRC supports two different compression regions, separated by a “Knee” at a specific input

amplitude. In the region above the knee, the compression slope [DRC]_HI_COMP applies; in the

region below the knee, the compression slope [DRC]_LO_COMP applies.

The DRC also supports a noise gate region, where low-level input signals are heavily attenuated. This

function can be enabled or disabled according to the application requirements. The DRC response in

this region is defined by the expansion slope [DRC]_NG_EXP.

For additional attenuation of signals in the noise gate region, an additional “knee” can be defined

(shown as “Knee2” in Figure 24). When this knee is enabled, this introduces an infinitely steep drop-

off in the DRC response pattern between the [DRC]_LO_COMP and [DRC]_NG_EXP regions.

The overall DRC compression characteristic in “steady state” (i.e. where the input amplitude is near-

constant) is illustrated in Figure 24.

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