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WM8994ECS/R Datenblatt(PDF) 66 Page - Cirrus Logic

Teilenummer WM8994ECS/R
Bauteilbeschribung  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8994ECS/R Datenblatt(HTML) 66 Page - Cirrus Logic

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WM8994
66
Rev 4.6
DIGITAL SIDETONE MIXING
There are two digital sidetone signal paths, STL and STR. The sidetone sources are selectable for
each path. The sidetone mixer outputs are inputs to the DAC signal mixers.
The following sources can be selected for sidetone path STL.
ADCL or DMICDAT1 (Left) channel
DMICDAT2 (Left) channel
The following sources can be selected for sidetone path STR.
ADCR or DMICDAT1 (Right) channel
DMICDAT2 (Right) channel
The sidetone signal sources are selected using STR_SEL and STL_SEL as described in Table 17.
Note that, when STR_SEL = 0 or STL_SEL = 0, and the respective ADC is enabled (for analogue
inputs), then the ADC data will be selected for applicable sidetone path.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1569 (0621h)
Sidetone
1
STR_SEL
0
Select source for sidetone STR path
0 = ADCR / DMICDAT1 (Right)
1 = DMICDAT2 (Right)
0
STL_SEL
0
Select source for sidetone STL path
0 = ADCL / DMICDAT1 (Left)
1 = DMICDAT2 (Left)
Table 17 Digital Sidetone Mixing
DIGITAL SIDETONE VOLUME AND FILTER CONTROL
A digital volume control is provided for the digital sidetone paths. The associated register controls are
described in Table 18.
A digital high-pass filter can be enabled in the sidetone paths to remove DC offsets. This filter is
enabled using the ST_HPF register bit; the cut-off frequency is configured using ST_HPF_CUT. When
the filter is enabled, it is enabled in both digital sidetone paths.
Note that the sidetone filter cut-off frequency scales according to the sample rate of AIF1 or AIF2.
When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the ST_HPF cut-off
frequency is scaled according to the AIF1_SR register. When AIF2CLK is selected as the SYSCLK
source (SYSCLK_SRC = 1), then the ST_HPF cut-off frequency is scaled according to the AIF2_SR
register. S
ee “Clocking and Sample Rates” for further details of the system clocks and control
registers.



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