WM8994ECSSLASHR datasheet(72/363 Pages) CIRRUS

72 / 363 page

WM8994

Rev 4.6

DYNAMIC RANGE CONTROL (DRC)

The Dynamic Range Control (DRC) is a circuit which can be enabled in the digital playback or digital

record paths of the WM8994 audio interfaces. The function of the DRC is to adjust the signal gain in

conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording

from microphones built into a handheld system.

The DRC can apply Compression and Automatic Level Control to the signal path. It incorporates ‘anti-

clip’ and ‘quick release’ features for handling transients in order to improve intelligibility in the

presence of loud impulsive noises.

The DRC also incorporates a Noise Gate function, which provides additional attenuation of very low-

level input signals. This means that the signal path is quiet when no signal is present, giving an

improvement in background noise level under these conditions.

The WM8994 provides three stereo Dynamic Range Controllers (DRCs); these are associated with

AIF1 timeslot 0, AIF1 timeslot 1 and AIF2 respectively. Each DRC can be enabled either in the DAC

playback (AIF input) path or in the ADC record (AIF out

put) path, as described in the “Digital Core

Architecture

” section.

The DRCs are enabled in the DAC or ADCs audio signal paths using the register bits described in

Table 22. Note that enabling any DRC in the DAC and ADC paths simultaneously is an invalid

selection.

When the DRC is enabled in any of the ADC (digital record) paths, the associated High Pass Filter

(HPF) must be enabled also; this ensures that DC offsets are removed prior to the DRC processing.

The output path HPF control registers are described in Table 36 (for AIF1 output paths) and Table 43

(for AIF2 output paths). These are described in the “Digital Volume and Filter Control” section.

Note that, when ultrasonic (4FS) mode is selected on AIF1, then the DRC function is bypassed on the

respective ADC (output) signal paths. The DRC may still be selected on the AIF1 DAC (input) signal

paths.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1088 (0440h)

AIF1 DRC1 (1)

AIF1DAC1_DRC

_ENA

Enable DRC in AIF1DAC1 playback

path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

AIF1ADC1L_DR

C_ENA

Enable DRC in AIF1ADC1 (Left)

record path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

AIF1ADC1R_DR

C_ENA

Enable DRC in AIF1ADC1 (Right)

record path (AIF1, Timeslot 0)

0 = Disabled

1 = Enabled

R1104 (0450h)

AIF1 DRC2 (1)

AIF1DAC2_DRC

_ENA

Enable DRC in AIF1DAC2 playback

path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

AIF1ADC2L_DR

C_ENA

Enable DRC in AIF1ADC2 (Left)

record path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

AIF1ADC2R_DR

C_ENA

Enable DRC in AIF1ADC2 (Right)

record path (AIF1, Timeslot 1)

0 = Disabled

1 = Enabled

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