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WM8994ECS/R Datenblatt(PDF) 65 Page - Cirrus Logic

Teilenummer WM8994ECS/R
Bauteilbeschribung  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8994ECS/R Datenblatt(HTML) 65 Page - Cirrus Logic

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WM8994
Rev 4.6
65
AUDIO INTERFACE 1 (AIF1) OUTPUT MIXING
There are four AIF1 digital mixers, one for each AIF1 audio channel (ie. Left/Right channels on
Timeslots 0/1). The inputs to each AIF1 mixer comprise signals from the ADC / Digital Microphone
inputs and from AIF2.
Note that the Left/Right channels of AIF1 can be inverted or interchanged if requ
ired; see “Digital
Audio Interface Control
”.
The AIF1 Left Timeslot 0 output channel is derived from the ADCL / DMIC1 (Left) and AIF2 (Left)
inputs. The ADCL / DMIC1 (Left) path is enabled by ADC1L_TO_AIF1ADC1L, whilst the AIF2 (Left)
path is enabled by AIF2DACL_TO_AIF1ADC1L.
The AIF1 Right Timeslot 0 output channel is derived from the ADCR / DMIC1 (Right) and AIF2 (Right)
inputs. The ADCR / DMIC1 (Right) path is enabled by ADC1R_TO_AIF1ADC1R, whilst the AIF2
(Right) path is enabled by AIF2DACR_TO_AIF1ADC1R.
The AIF1 Left Timeslot 1 output channel is derived from the DMIC2 (Left) and AIF2 (Left) inputs. The
DMIC2 (Left) path is enabled by ADC2L_TO_AIF1ADC2L, whilst the AIF2 (Left) path is enabled by
AIF2DACL_TO_AIF1ADC2L.
The AIF1 Right Timeslot 1 output channel is derived from the DMIC2 (Right) and AIF2 (Right) inputs.
The DMIC2 (Right) path is enabled by ADC2R_TO_AIF1ADC2R, whilst the AIF2 (Right) path is
enabled by AIF2DACR_TO_AIF1ADC2R.
The AIF1 output mixer controls are defined in Table 16.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1542 (0606h)
AIF1 ADC1
Left Mixer
Routing
1
ADC1L_TO_AIF
1ADC1L
0
Enable ADCL / DMIC1 (Left) to
AIF1 (Timeslot 0, Left) output
0 = Disabled
1 = Enabled
0
AIF2DACL_TO_
AIF1ADC1L
0
Enable AIF2 (Left) to AIF1 (Timeslot
0, Left) output
0 = Disabled
1 = Enabled
R1543 (0607h)
AIF1 ADC1
Right Mixer
Routing
1
ADC1R_TO_AIF
1ADC1R
0
Enable ADCR / DMIC1 (Right) to
AIF1 (Timeslot 0, Right) output
0 = Disabled
1 = Enabled
0
AIF2DACR_TO_
AIF1ADC1R
0
Enable AIF2 (Right) to AIF1
(Timeslot 0, Right) output
0 = Disabled
1 = Enabled
R1544 (0608h)
AIF1 ADC2
Left Mixer
Routing
1
ADC2L_TO_AIF
1ADC2L
0
Enable DMIC2 (Left) to AIF1
(Timeslot 1, Left) output
0 = Disabled
1 = Enabled
0
AIF2DACL_TO_
AIF1ADC2L
0
Enable AIF2 (Left) to AIF1 (Timeslot
1, Left) output
0 = Disabled
1 = Enabled
R1545 (0609h)
AIF1 ADC2
Right Mixer
Routing
1
ADC2R_TO_AIF
1ADC2R
0
Enable DMIC2 (Right) to AIF1
(Timeslot 1, Right) output
0 = Disabled
1 = Enabled
0
AIF2DACR_TO_
AIF1ADC2R
0
Enable AIF2 (Right) to AIF1
(Timeslot 1, Right) output
0 = Disabled
1 = Enabled
Table 16 AIF1 Output Mixing



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