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WM8994ECS/R Datenblatt(PDF) 50 Page - Cirrus Logic

Teilenummer WM8994ECS/R
Bauteilbeschribung  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8994ECS/R Datenblatt(HTML) 50 Page - Cirrus Logic

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WM8994
50
Rev 4.6
INPUT PGA VOLUME CONTROL
Each of the four Input PGAs has an independently controlled gain range of -16.5dB to +30dB in 1.5dB
steps. The gains on the inverting and non-inverting inputs to the PGAs are always equal. Each Input
PGA can be independently muted using the PGA mute bits as described in Table 4, with maximum
mute attenuation achieved by simultaneously disconnecting the corresponding inputs described in
Table 3.
Note that, under default conditions (following power-up or software reset), the PGA mute register bits
are set to ‘1’, but the mute functions will only become effective after the respective bit has been
toggled to ‘0’ and then back to ‘1’. The Input PGAs will be un-muted (Mute disabled) after power-up or
software reset, regardless of the readback value of the respective PGA mute bits.
To prevent "zipper noise", a zero-cross function is provided on the input PGAs. When this feature is
enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long
period without zero-crossings, a timeout function is provided. When the zero-cross function is
enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The
timeout clock is enabled using TOCLK_ENA, the timeout period is set by TOCLK_DIV
. See “Clocking
and Sample Rates
” for more information on these fields.
The IN1_VU and IN2_VU bits control the loading of the input PGA volume data. When IN1_VU and
IN2_VU are set to 0, the PGA volume data will be loaded into the respective control register, but will
not actually change the gain setting. The IN1L and IN1R volume settings are both updated when a 1
is written to IN1_VU; the IN2L and IN2R volume settings are both updated when a 1 is written to
IN2_VU. This makes it possible to update the gain of the left and right signal paths simultaneously.
The Input PGA Volume Control register fields are described in Table 4 and Table 5.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24 (0018h)
Left Line Input
1&2 Volume
8
IN1_VU
N/A
Input PGA Volume Update
Writing a 1 to this bit will cause IN1L and
IN1R input PGA volumes to be updated
simultaneously
7
IN1L_MUTE
1
IN1L PGA Mute
0 = Disable Mute
1 = Enable Mute
6
IN1L_ZC
0
IN1L PGA Zero Cross Detector
0 = Change gain immediately
1 = Change gain on zero cross only
4:0
IN1L_VOL
[4:0]
01011
(0dB)
IN1L Volume
-16.5dB to +30dB in 1.5dB steps
(See Table 5 for volume range)
R25 (0019h)
Left Line Input
3&4 Volume
8
IN2_VU
N/A
Input PGA Volume Update
Writing a 1 to this bit will cause IN2L and
IN2R input PGA volumes to be updated
simultaneously
7
IN2L_MUTE
1
IN2L PGA Mute
0 = Disable Mute
1 = Enable Mute
6
IN2L_ZC
0
IN2L PGA Zero Cross Detector
0 = Change gain immediately
1 = Change gain on zero cross only
4:0
IN2L_VOL
[4:0]
01011
(0dB)
IN2L Volume
-16.5dB to +30dB in 1.5dB steps
(See Table 5 for volume range)



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