WM8994ECSSLASHR datasheet(171/363 Pages) CIRRUS

171 / 363 page

WM8994

Rev 4.6

171

AUDIO DATA FORMATS (TDM MODE)

TDM is supported in master and slave modes. All audio interface data formats support time division

multiplexing (TDM) for ADC and DAC data.

When more than one pair of ADC or DAC data channels is enabled on AIF1, the WM8994 will transmit

and receive data in both Slot 0 and Slot 1.

In the case of AIF2, the ADC or DAT data can be transmitted or received in either timeslot; the

required timeslot is selected using register control bits when TDM is enabled.

When TDM is enabled, the ADCDAT pin will be tri-stated immediately before and immediately after

data transmission, to allow another ADC device to drive this signal line for the remainder of the

sample period. Note that it is important that two ADC devices do not attempt to drive the data pin

simultaneously. A short circuit may occur if the transmission time of the two ADC devices overlap with

each other. See “Audio Interface Timing” for details of the ADCDAT output relative to BCLK signal.

Note that it is possible to ensure a gap exists between transmissions by setting the transmitted word

length to a value higher than the actual length of the data. For example, if 32-bit word length is

selected where only 24-bit data is available, then the WM8994 interface will tri-state after transmission

of the 24-bit data, ensuring a gap after the WM8994 TDM slot.

On AIF1, TDM can be used to transmit or receive up to four signal paths. Each enabled signal path is

transmitted (on ADCDAT) or received (on DACDAT) sequentially. If one or more of the signal paths is

disabled, then the position of remaining data blocks within the LRCLK frame may differ from those

illustrated in Figure 57 to Figure 61, as the

affected channel(s) will revert to the ‘normal’ (non-TDM)

format. When the AIF1ADC_TDM register is set, then the ADCDAT1 output is tri-stated when not

outputting data.

On AIF2, the TDM format is enabled by register control (AIF2ADC_TDM and AIF2DAC_TDM for the

output and input paths respectively). When TDM is enabled on AIF2, the data formats shown in Figure

57 to Figure 61 are always selected, and the WM8994 transmits or receives data in one of the two

available timeslots; the ADCDAT2 output is tri-stated when not outputting data.

In all cases, the BCLK frequency must be high enough to allow data from the relevant time slots to be

transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format; the TDM

timing for four input or output channels is shown in Figure 57 to Figure 61.

SLOT 0

LEFT CHANNEL

RIGHT CHANNEL

1/fs

LRCLK

BCLK

DACDAT/

ADCDAT

SLOT 1

SLOT 0

SLOT 1

Figure 57 TDM in Right-Justified Mode

LEFT CHANNEL

RIGHT CHANNEL

1/fs

LRCLK

BCLK

DACDAT/

ADCDAT

SLOT 0

SLOT 1

SLOT 0

SLOT 1

Figure 58 TDM in Left-Justified Mode

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