WM8994ECSSLASHR datasheet(176/363 Pages) CIRRUS

176 / 363 page

WM8994

176

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R768 (0300h)

AIF1 Control

(1)

AIF1_BCLK

_INV

BCLK1 Invert

0 = BCLK1 not inverted

1 = BCLK1 inverted

Note that AIF1_BCLK_INV selects the BCLK1

polarity in Master mode and in Slave mode.

AIF1_LRCL

K_INV

Right, left and I2S modes

– LRCLK1 polarity

0 = normal LRCLK1 polarity

1 = invert LRCLK1 polarity

Note that AIF1_LRCLK_INV selects the

LRCLK1 polarity in Master mode and in Slave

mode.

DSP Mode

– mode A/B select

0 = MSB is available on 2nd BCLK1 rising

edge after LRCLK1 rising edge (mode A)

1 = MSB is available on 1st BCLK1 rising

edge after LRCLK1 rising edge (mode B)

R771 (0303h)

AIF1 BCLK

8:4

AIF1_BCLK

_DIV [4:0]

00100

BCLK1 Rate

00000 = AIF1CLK

00001 = AIF1CLK / 1.5

00010 = AIF1CLK / 2

00011 = AIF1CLK / 3

00100 = AIF1CLK / 4

00101 = AIF1CLK / 5

00110 = AIF1CLK / 6

00111 = AIF1CLK / 8

01000 = AIF1CLK / 11

01001 = AIF1CLK / 12

01010 = AIF1CLK / 16

01011 = AIF1CLK / 22

01100 = AIF1CLK / 24

01101 = AIF1CLK / 32

01110 = AIF1CLK / 44

01111 = AIF1CLK / 48

10000 = AIF1CLK / 64

10001 = AIF1CLK / 88

10010 = AIF1CLK / 96

10011 = AIF1CLK / 128

10100 = AIF1CLK / 176

10101 = AIF1CLK / 192

10110 - 11111 = Reserved

R772 (0304h)

AIF1ADC

LRCLK

AIF1ADC_L

RCLK_DIR

Allows ADCLRCLK1 to be enabled in Slave

mode

0 = Normal

1 = ADCLRCLK1 enabled in Slave mode

10:0

AIF1ADC_R

ATE [10:0]

040h

ADCLRCLK1 Rate

ADCLRCLK1 clock output =

BCLK1 / AIF1ADC_RATE

Integer (LSB = 1)

Valid from 8..2047

WM8994ECS/R Datenblatt(PDF) 176 Page - Cirrus Logic

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