WM8994ECSSLASHR datasheet(284/363 Pages) CIRRUS

284 / 363 page

WM8994

284

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R517 (0205h)

AIF2

Clocking (2)

5:3

AIF2DAC_DIV

[2:0]

000

Selects the AIF2 input path sample rate relative to the AIF2

output path sample rate.

This field should only be changed from default in modes

where the AIF2 input path sample rate is slower than the

AIF2 output path sample rate.

000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved

2:0

AIF2ADC_DIV

[2:0]

000

Selects the AIF2 output path sample rate relative to the

AIF2 input path sample rate.

This field should only be changed from default in modes

where the AIF2 output path sample rate is slower than the

AIF2 input path sample rate.

000 = Divide by 1

001 = Divide by 1.5

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5.5

110 = Divide by 6

111 = Reserved

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R520 (0208h)

Clocking (1)

TOCLK_ENA

Slow Clock (TOCLK) Enable

0 = Disabled

1 = Enabled

This clock is required for zero-cross timeout.

AIF1DSPCLK_E

AIF1 Processing Clock Enable

0 = Disabled

1 = Enabled

AIF2DSPCLK_E

AIF2 Processing Clock Enable

0 = Disabled

1 = Enabled

SYSDSPCLK_E

Digital Mixing Processor Clock Enable

0 = Disabled

1 = Enabled

SYSCLK_SRC

SYSCLK Source Select

0 = AIF1CLK

1 = AIF2CLK

WM8994ECS/R Datenblatt(PDF) 284 Page - Cirrus Logic

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