ST7285C datasheet(63/117 Pages) STMICROELECTRONICS

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ST7285C

2C BUS INTERFACE (Cont’d)

Transfer sequencing:

Master transmitter: (M/SL=1)

IT1: SB =1. This interrupt is cleared by a read of SR1 followed by a write in DR.

IT2: This interrupt is cleared by a read of SR1 followed by a write in CR and in DR.

IT3: BTF=1; TRA=1. This interrupt is cleared by a read of SR1 followed by a write in DR.

Master receiver: (M/SL=1)IT4: This interrupt is cleared by a read of SR1 followed by a write in CR.

IT5: BTF=1. This interrupt is cleared by a read of SR1 followed by a read of DR.

Slave transmitter: (M/SL=0)

IT6: ADSL =1. This interrupt is cleared by a read of SR1 followed by a write in DR.

IT7: BTF=1, TRA=1. This interrupt is cleared by a read of SR1 followed by a write in DR.

IT8: StopF=1. This interrupt is cleared by a read of SR2.

Slave receiver: (M/SL=0)

IT9: ADSL =1. This interrupt is cleared by a read of SR1.

IT10: BTF=1. This interrupt is cleared by a read of SR1 followed by a read of DR.

10 bits addressing (Master):

Master:

IT11: ADD10=1. This interrupt is cleared by a read of SR1 followed by a write in DR.

Slave:

During IT1,2,3,4,5,6,7,9,10,11 the SCL line is hold low.

S: Start; P: Stop; A: Acknowledge; IT: interrupt.

Detailed timing information is available in the ELECTRICAL CHARACTERISTICS.

IT1

ADD

IT2

IT3

DATA

IT3

DATA

IT3

IT1

ADD

IT4

DATA

IT5

DATA

IT5

ADD

IT6

IT7

DATA

IT7

DATA

IT7

IT8

ADD

IT9

DATA

IT10

DATA

IT10

IT8

ADD

IT11

ADD

IT2

ADD

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