ST7285C datasheet(47/117 Pages) STMICROELECTRONICS

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ST7285C

SERIAL PERIPHERAL INTERFACE(Cont’d)

4.4.4 Signal Description

The four basic signals (MOSI, MISO, SCK andSS)

are described in the following paragraphs. Each

signal function is described for both the Master

and Slave mode.

The SPE (Serial Peripheral Enable) bit of the SPI

Control Register enables and disables the SPI (ac-

tive high); when the SPI is enabled the associated

alternate functions will be attributed to the relevant

I/O pins.

The SPI baud rate is the CPU clock divided by a

factor defined by software (2, 4, 16, 32).

4.4.5 Master Out Slave In (MOSI)

The MOSI pin is configured as a data output in the

Master (mode) device and as a data input in the

Slave (mode) device.

In this manner data is transferred serially from a

Master to a Slave on this line, most significant bit

first, least significant bit last. The timing diagrams

shown in the ELECTRICAL CHARACTERISTICS

section, CONTROL TIMING subsection, illustrate

SPI timing and show the relationship between data

and clock (SCK).

Four possible timing relationships may be chosen

by using control bits CPOL and CPHA. The Master

device always allows data to be applied on the

MOSI line a half-cycle before the clock edge

(SCK) to allow the Slave device to latch the data.

Both the Slave device(s) and a Master device

must be programmed to similar modes for proper

data transfer.

When the Master device transmits data to a sec-

ond (Slave) device via the MOSI line, the Slave

device responds by sending data to the Master de-

vice via the MISO line. This implies full duplex

transmission with both data out and data in syn-

chronized with the same clock signal (which is pro-

vided by the Master device). Thus, the byte trans-

mitted is replaced by the byte received and elimi-

nates the need for separate transmit-empty and

receiver-full status bits. A single status bit SPIF) is

used to signify that the I/O operation is complete.

Configuration of the MOSI pin is a function of the

MSTR bit in the Serial Peripheral Control Register

(SPCR). When operating as a Master, the user

should set the MSTR bit, defining the MOSI pin as

an output

4.4.6 Master In Slave Out (MISO)

The MISO pin is configured as an input in a Master

(mode) device and as an output in a Slave (mode)

device. In this manner data is transferred serially

from a Slave to a Master on this line, most signifi-

cant bit first, least significant bit last. The MISO pin

of a Slave device is placed in the high-impedance

state if it is not selected by the Master, i.e. itsSS

pin is at a logic high level. The timing diagram

shows the relationship between data and clock

(SCK). Four possible timing relationships may be

chosen by using control bits CPOL and CPHA. The

Master device always allows data to be applied on

the MOSI line a half-cycle before the clock edge

(SCK) in order for the Slave device to latch the da-

ta.

Note. The Slave device and a Master device must

be programmed with similar timing modes for

proper data transfer.

When the Master device transmits data to a Slave

device via the MOSI line, the Slave device re-

sponds by sending data to Master device via the

MISO line. This implies full duplex transmission

with both data out and data in synchronized with

the same clock signal (one which is provided by

the Master device.) Thus, the byte transmitted is

replaced by the byte received and eliminates the

need for separate transmit-empty and receiver-full

bits. A single status bit (SPIF) in the Serial Periph-

eral Status Register (SPSR) is used to signify that

the I/O operation is complete.

In the Master device, the MSTR control bit in the

Serial Peripheral Control Register (SPCR) should

be set (by the program) to allow the Master device

to receive data on its MISO pin. In the Slave de-

vice, its MISO pin is enabled by the logic high level

present on the SS pin: i.e. if SS = 1 the MISO pin is

placed in the high-impedance state, whereas ifSS

= 0 the MISO pin is an output for the Slave device.

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