ST7285C datasheet(15/117 Pages) STMICROELECTRONICS

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ST7285C

3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES

3.1 CLOCK SYSTEM

3.1.1 General Description

The MCU accepts either a Crystal or Ceramic res-

onator, or an external clock signal to drive the in-

ternal oscillator. The internal clock (CPU CLK run-

ning at fCPU) is derived from the external oscillator

frequency (fOSC). The external Oscillator clock is

first divided by 2, and an additional division factor

of 2, 4, 8, or 16 can be applied, in Slow Mode, to

reduce the frequency of the CPU clock (see

note 1); this clock signal is also routed to the on-

chip peripherals. The CPU clock signal consists of

a square wave with a duty cycle of 50%.

Figure 4. External Clock Source Connections

Figure 5. Equivalent Crystal Circuit

3.1.2 Crystal Resonator

The internal oscillator is designed to operate with

an AT-cut parallel resonant quartz crystal resona-

tor in the frequency range specified for fosc.The

circuit shown in Figure 6 is recommended when

using a crystal, and Table 2 lists the recommend-

ed capacitance and feedback resistance values.

The crystal and associated components should be

mounted as close as possible to the input pins in

order to minimize output distortion and start-up

stabilisation time.

Use of an external CMOS oscillator is recom-

mended when crystals outside the specified fre-

quency ranges are to be used.

Figure 6. Crystal/Ceramic Resonator

Figure 7. Clock Prescaler Block Diagram

Note 1: Additional division factor of CPU clock is only available on L5/L6.

OSCin

OSCout

EXTERN AL

CLOCK

OSCin

OSCout

OSCin

OSCout

COSCin

COSCout

OSCin

OSCout

COSCin

COSCout

%2,4,8,16

CPUCLK

to CPU and

Peripherals

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