ST7285C datasheet(52/117 Pages) STMICROELECTRONICS

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ST7285C

SERIAL PERIPHERAL INTERFACE(Cont’d)

The second collision mode is defined by the CPHA

control bit being set. With the CPHA bit set, the

Slave device will be receiving a clock (SCK) edge

prior to the latch of the first data transfer. This first

clock edge will freeze the data in the Slave device

I/O register and allow the msb on to the external

MISO pin of the Slave device. A logic low state on

the SS pin enables the Slave device, however,

data is not output on the MISO pin until the first

edge of the data transfer clock. The WCOL bit will

only be set if the I/O register is accessed while a

transfer is taking place. In this second collision

mode, a Master device can hold a Slave device’s

SS pin low during the transfer of several bytes of

data without this causing any problems.

Unlike other SPI interfaces, there is no special

case of collision which remains undetected by

the WCOL bits. The WCOL bit is TOTALLY reli-

able with regard to collision detection.

Since the Slave device is operating asynchronous-

ly with the Master device, the WCOL bit may be

used as an indicator of a collision occurence. This

helps alleviate the user from a strict real-time pro-

gramming effort. The WCOL is cleared on Reset.

Bit-4 = MODF

Mode Fault flag

The function of the mode fault flag is defined for

the Master mode (device). If the device is a Slave

device the MODF bit will be prevented from tog-

gling from reset to set; however, this does not pre-

vent the device from being in the Slave mode with

the MODF bit set.

The MODF bit is normally reset, and is set only

when the Master device has itsSS pin pulled low.

Toggling the MODF bit to the set state affects the

internal Serial Peripheral Interface (SPI) system in

the following ways:

a) MODF is set and SPI interrupt is generated if

SPIE is set.

b) The SPE bit is forced to a reset state. This

blocks all output from the device and disables the

SPI system.

c) The MSTR bit is forced to a reset state, thus

forcing the device into the Slave mode.

Clearing the MODF is accomplished by a software

sequence which accesses the Serial Peripheral

Status Register while MODF is set, followed by a

write to the Serial Peripheral Control Register.

To avoid multiple Slave conflicts in a system com-

prising several MCUs, the SS pin must be pulled

high during the clearing sequence of MODF. Con-

trol bits SPE and MSTR may be restored to their

original set state during this clearing sequence, or

after the MODF bit has been cleared. Hardware

does not allow the user to set the SPE and MSTR

bits while MODF is set, unless this occurs during

the proper clearing sequence. The MODF flag bit

indicates the possible occurrence of a Multimaster

conflict for system control, and allows proper exit

from normal system operation to Reset or to a de-

fault system state. The MODF bit is cleared on Re-

set.

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