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ST7285C

4.5 I

2C BUS INTERFACE

4.5.1 Introduction

The I

2C Bus Interface serves as an interface be-

tween the MCU and the serial I2C bus. It provides

both multimaster and multislave functions, and

controls all I

2C bus-specific sequencing, protocol,

arbitration and timing.

4.5.2 General Features

– Parallel bus /I

2C protocol converter

– Multi-Master capability

– Interrupt generation

– Standard I

2C mode/Fast I2Cmode

– 7-bit Addressing/10-bit Addressing

4.5.2.1 I

2C Master Mode Features:

– Flag indicating when the I

2C bus is in use

– Flag indicating the loss of arbitration

– Flag indicating the end of the byte transmission

– Transmitter/Receiver flag

– Clock generation

4.5.2.2 I

2C Slave Mode Features:

– Start bit detection flag

– Detection of a misplaced Start or Stop condition

– Detection of a problem during transfer

– Address Matched detection

– General call detection

– Flag indicating the end of the byte transmission

– Transmitter/Receiver flag

4.5.3 Functional Description

In addition to receiving and transmitting data, this

interface converts it from serial to parallel format

and vice versa, using either an interrupt or polled

handshake. The interrupts are enabled or disabled

by software. The interface is connected to the I

bus by a data pin (SDA) and by a clock pin (SCL).

It can be connected both with a standard I2C bus

and a Fast I

2C bus. This selection is made by soft-

ware.

The interface can operate in the four following

modes:

– Master transmitter

– Master receiver

– Slave transmitter

– Slave receiver

When it is inactive, it operates in Slave Mode.

This interface enables the multimaster function

thanks to an automatic switch between Master and

Slave mode in the event of a loss of arbitration:the

Slave process is always active when a start condi-

tion is detected on the SDA line. When acting as

Master, it initiates a data transfer and generates

the clock signal. A serial data transfer always be-

gins with a start condition and ends with a stop

condition. Both start and stop conditions are soft-

ware generated in Master mode. In Slave mode,

the interface is capable of recognising its own ad-

dress (7-bit or 10-bit), a general call address or a

start byte. The general call may be enabled or dis-

abled by software.

Data and addresses are transferred as 8-bit bytes,

MSB first. The first byte following the start condi-

tion in 7-bit addressing (two first bytes in 10-bit ad-

dressing) is the address byte; it is always transmit-

ted in Master mode. A 9th clock pulse follows the 8

clock cycles of a byte transfer, during which the re-

ceiver must send an acknowledge bit to the trans-

mitter. Acknowledge may be enabled and disabled

by software.

When in Transmitter mode, the interface waits for

the MCU to write the byte in the Data Register, by

holding the clock line low before transmission;

when in Receiver mode, it waits for the MCU to

read the byte in the Data Register by holding the

clock line low after reception.

The I

2C Bus Interface has seven internal registers.

Three of these are used for interface initialization

(Own Address Registers and Clock Control Regis-

ter). The remaining four registers are used during

data transmission/reception (Data Register, Con-

trol Register and Status Register).

The SCL frequency (Fscl) is controlled by a pro-

grammable clock divider which depends on the

2C bus mode. The I2C interface address is stored

in two registers (OAR) in order to allow 10-bit ad-

dressing.

The Peripheral Enable bit (bit 6) of the I

2C Control

the I/O as I

2C pins. The speed of the I2C interface

may be selected between 100KHz and 400KHz.

When the I

2C cell is enabled, PA4 and PA6 are

configured as open-drain. In this case, the external

pull-up resistance should be 10K

Ω or more.

When the I

2C cell is disabled, PA4 and PA6 revert

to being standard I/ O port pins.

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