ST7285C datasheet(43/117 Pages) STMICROELECTRONICS

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ST7285C

16-BIT TIMER (Cont’d)

4.3.6 Timer Registers

As can be seen from the Memory Map, each Timer

is associated with three control and status regis-

ters which are described in detail below, as well as

with six pairs of data registers (16-bit values) relat-

ing to the two input captures, the two output com-

pares, the counter and the alternate counter.

These six pairs of data registers are self-explana-

tory and need no further description.

TIMER CONTROL REGISTER 1 (TCR1)

Address: see Memory Map

—

Read/Write

Reset Value: 0000 0000b

Bit 7 = ICIE

Input Capture Interrupt Enable

If ICIE is set, a timer interrupt is enabled whenever

the ICF1 or ICF2 status flags of TSR are set. If the

ICIE bit is cleared, the interrupt is inhibited.

Bit 6 = OCIE

Output Compare Interrupt Enable

If OCIE is set, a timer interrupt is enabled whenev-

er the OCF1 or OCF2 status flags of TSR are set.

If the OCIE bit is cleared, the interrupt is inhibited.

Bit 5 = TOIE

Timer Overflow Interrupt Enable

If TOIE is set, a timer interrupt is enable whenever

the TOF status flag of TSR is set. If the TOIE bit is

cleared, the interrupt is inhibited.

Bit 4 = FOLV2

Forced Output Compare 2

When written to 1, FOLV2 forces OLVL2 to be

copied to the OCMP2 pin. FOLV2 has no effect

otherwise. It can only be reset by a system reset.

Bit 3 = FOLV1

Forced Output Compare 1

When written to 1, FOLV1 forces OLVL1 to be

copied to the OCMP1 pin. FOLV1 has no effect

otherwise. It can only be reset by a System Reset.

Bit 2 = OLVL2 Output Level 2

The OLVL2 bit is copied to the OCMP2 pin when-

ever a successful comparison occurs at OCR2.

Bit 1 = IEDG1 Input Edge 1

The value of IEDG1 determines which type of level

transition on pin ICAP1 will trigger a free running

counter transfer to the ICR1. When IEDG1 is set, a

rising edge triggers the capture, and when it is re-

set, a falling edge does.

Bit 0 = OLVL1

Output Level 1

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs at OCR1.

TIMER CONTROL REGISTER 2 (TCR2)

Address: see Memory Map

—

Read/Write

Reset Value: 0000 0000b

Bit 7 = OC1E

Output Compare 1 Enable

If OC1E is set, the Output Compare 1 pin

(OCMP1) is dedicated to the output compare 1 ca-

pability of the timer. If OC1E is reset, this pin is a

general use I/O pin.

Bit 6 = OC2E

Output Compare 2 Enable

If OC2E is set, the output compare 2 pin (OCMP2)

is dedicated the output compare 2 capability of the

timer. If OC2E is reset, this is a general I/O pin.

Bit 5 = OPM

One Pulse Mode

If OPM is set, the input pin ICAP1 is usable to trig-

ger one pulse on the output pin OCMP1; the active

transition on ICAP1 is given by the state of IEDG1.

The length of the generated pulse depends on the

the contents of OCR1.

Bit 4 = PWM

Pulse Width Modulation

If PWM is set, the output pin OCMP1 outputs a

programmable cyclic signal; the length of the pulse

depends on the value of OCR1; the period de-

pends on the value of OCR2.

Bit 3, 2 = CC1-CC0

Clock Control

00: the internal clock is divided by 4

01: the internal clock is divided by 2

10: the internal clock is divided by 8

11: the external clock is selected as shown

in the Block Diagram.

Bit 1 = IEDG2 Input Edge 2

The value of IEDG2 determines which level transi-

tion on pin ICAP2 will trigger the free running

counter transfer to the ICR2. When IEDG2 is high,

a rising edge triggers the capture since when low,

a falling edge does.

Bit 0 = EXEDG

External Clock Edge

The status of EXEDG determines which type of

level transition on the external clock pin EXCLK

will trigger the free running counter. When EXEDG

is set, the active transition is the rising edge; when

EXEDG is reset, the active transition is the falling

edge.

ICIE

OCIE

TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

OC1E

OC2E

OPM

PWM

CC1

CC0

IEDG2

EXEDG

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