ST7285C datasheet(40/117 Pages) STMICROELECTRONICS

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ST7285C

16-BIT TIMER (Cont’d)

4.3.5 Output Compare

Two output compare registers are present: Output

Compare Register 1 and Output Compare Regis-

ter 2 (OCR1 and OCR2). These registers can be

used for several purposes, such as controlling an

output waveform or indicating when a period of

time has elapsed. The OCMP

i pin is associated

with the Output Compare

i function (i = 1 or 2).

The Output Compare Registers are unique in that

all bits are readable and writable and are not af-

fected by the timer hardware or by Reset. If a com-

pare function is not used, the two bytes of the cor-

responding Output Compare Registers can be

used as general purpose storage locations.

4.3.5.1 Output Compare Registers

The Output Compare Register

i (OCRi) is a 16-bit

the most significant byte register (OCHR

i) and the

least significant byte register (OCLR

i).

In this section, the index,

i, may be 1 or 2.

The content of OCR

i is compared with the content

of the free running counter once during every timer

clock cycles, i.e. once every 8, 4 or 2 internal proc-

essor clock periods or 2 external clock periods ac-

cording to the clock control bits of the Timer Con-

trol Register (TCR2). If match is found, the Output

Compare Flag OCF

i of the TSR is set and the Out-

put Level bit (OLVL

i) of the TCR1 is clocked to the

OCMP

i pin (see output compare timing diagrams

Figure 6, Figure 7, Figure 8). OLVL

i is copied to

the corresponding output level latch and hence, to

the OCMP

i pin regardless of whether the Output

Compare Flag (OCF

i) is set or not. The value in

the OCR

i and the OLVLi bit should be changed af-

ter each successful comparison in order to control

an output waveform or establish a new elapsed

timeout.

An interrupt accompanies a successful output

compare if the corresponding interrupt enable bit

OCIE of the TCR1 is set, provided the I-bit of the

CCR is cleared. Otherwise, the interrupt remains

pending until both conditions are true. It is cleared

by a read of TSR followed by an access to the LSB

of the OCR

After a processor write cycle to the OCHR

i regis-

ter, the output compare function is inhibited until

the OCLR

i is also written. Thus, the user must

write both bytes if the MSB is written first. A write

made to only the LSB will not inhibit the compare

function. The minimum time between two succes-

sive edges on the OCMP

i pin is a function of the

software program and the clock control bits of the

TCR2.

The OCMP

i output latch is forced low during reset

and stays low until valid compares change it to a

high level. Because the OCF

i flag and the OCRi

are undeterminate at power-on and are not affect-

ed by an external reset, care must be exercise

when initiating the output compare function with

software. The following procedure is recommend-

ed to prevent the OCF

i flag from being set be-

tween the time it is read and the write to OCR

– Write to OCHR

i (further compares are inhibited).

– Read the TSR (first step of the clearance of OC-

i, which may be already set).

– Write to OCLR

i (enables the output compare

function and clears OCF

i).

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