ST7285C datasheet(45/117 Pages) STMICROELECTRONICS

45 / 117 page

45/117

ST7285C

4.4 SERIAL PERIPHERAL INTERFACE

4.4.1 Introduction

The Serial Peripheral Interface (SPI) allows devic-

es to be interconnected using a minimum of wires.

The SPI is synchronous and thus uses a data and

a clock signal; in complex arrays, chip select lines

may also be used. An SPI system may be config-

ured as a Master and one or more Slaves, or as a

system in which devices may be either Masters or

Slaves. Depending on MCU specifications, one or

more SPIs may be present.

4.4.2 Features

– Full duplex, three-wire synchronous transfers

– Master or Slave operation

– 2 MHz (maximum) Master bit frequency

– 4 MHz (maximum) Slave bit frequency

– Four programmable Master bit rates

– Programmable clock polarity and phase

– End of transmission interrupt flag

– Write collision flag protection

– Master mode fault protection capability.

4.4.3 Functional Description

A block diagram of the Serial Peripheral Interface

(SPI) is shown in Figure 27. In a Master configura-

tion, the Master start logic receives an input from

the CPU (in the form of a write to the SPI rate gen-

erator data register) and originates the system

clock (SCK) based on the internal processor

clock. This clock is also used internally to control

the state controller as well as the 8-bit shift regis-

ter.

As a Master device, data is parallel loaded into the

8-bit shift register (from the internal bus) during a

write cycle, and then shifted out serially via the

MOSI pin to the Slave device(s). During a read cy-

cle, data is received serially from a Slave device

via the MISO pin and loaded into to the 8-bit shift

data is parallel transferred to the read buffer and

then made available to the internal data bus during

a CPU read cycle.

In Slave configuration, the Slave start logic re-

ceives a logic low level (from a Master device) on

the SS pin, and a system clock input (from the

same Master device) on the SCK pin. Thus, the

Slave is synchronized with the Master. Data from

the Master is received serially on the Slave MOSI

pin and is loaded into the 8-bit shift register.

Once the 8-bit shift register is loaded, its data is

parallel transferred to the read buffer and then is

made available to the internal data bus during a

CPU read cycle. During a write cycle, data is par-

allel loaded into the 8-bit shift register from the in-

ternal data bus and then shifted out serially to the

MISO pin for application to the Master device.

Figure 29 illustrates the MOSI, MISO and SCK

Master-Slave interconnections. Note that the Mas-

ter SS pin is tied to a logic high level and the Slave

SS pin to a logic low level.

Three registers are associated with each SPI inter-

face: the Serial Peripheral

Control Register

(SPCR), the Serial Peripheral Status Register

(SPSR), and the Serial Peripheral Data I/O regis-

ter (SPDR). These provide Control, Status, and

Data functions. These registers are described in

detail in the following pages.

ST7285C Datenblatt(PDF) 45 Page - STMicroelectronics

ST7285C Datenblatt(HTML) 45 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL