ST7285C datasheet(60/117 Pages) STMICROELECTRONICS

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ST7285C

2C BUS INTERFACE (Cont’d)

STATUS REGISTER 1 (SR1)

Address: 0029h

—

Read Only

Reset Value: 00h

b7: SR2F

Status Register 2 Flag

SR2F is set when at least one flag in the Status

are reset.

b6: ADD10

10 bit Master Addressing Mode

ADD10 is set when the 10 bit addressing mode

header (”11110xxx”) is sent as the first address

byte. When this bit is set, an interrupt is sent to the

microcontroller if ITE is set

This bit is cleared by a read of the Status Register,

followed by a write in the Data Register. It is also

cleared when the peripheral is disabled (PE=0) or

by reset.

b5: TRA

Transmitter/Receiver

TRA is set when the interface is in data transmis-

sion mode.

It is cleared by the detection of a stop condition, by

a loss of the bus arbitration (ARLO set). It is also

cleared when the peripheral is disabled (PE=0) or

by reset.

b4: BUSY

Bus Busy

BUSY bit is active when there is a communication

in progress on line.

The detection of the communications is always ac-

tive (even if the peripheral s disabled).

This bit is set by the detection of a Start condition

and it is cleared by the detection of a Stop condi-

tion or by reset.

b3: BTF

Byte Transfer Finished

- In transmitter mode, BTF bit is set after the trans-

mission of a data byte and an acknowledge clock

pulse.

It is cleared by a read of the Status Register (with

BTF set), followed by a write in the Data Register.

In receiver mode, BTF bit is set after the reception

of the acknowledge of a byte.

It is cleared by a reading of the Status Register

(with BTF set), followed by a read of the Data Reg-

ister.

It is also cleared when the peripheral is disabled

(PE=0) or by reset.

When BTF is set, the I

2C interrupt occurs if ITE is

set. Then the microcontroller must access the data

b2: ADSL

Addressed as Slave

ADSL bit is set when the address comparator rec-

ognizes either its own Slave address or the gener-

al call address. When this bit is set , an interrupt is

sent to the microcontroller if ITE is set.

This bit is cleared by a read of the status register

(when ADSL is set). It is also cleared when the pe-

ripheral is disabled (PE=0) or by reset.

b1: M/SL Master/Slave

M/SL bit is set when the interface generates a

Start condition. When it is set, the interface oper-

ates in Master mode.

It is cleared by the detection of a Stop condition,

by a loss of arbitration, by reset or when the pe-

ripheral is disabled (PE=0).

b0: SB

Start Bit ( in Master mode)

In Master mode , SB bit is set when the hardware

has generated a Start condition. When this bit is

set, an interrupt is sent to the microcontroller if ITE

is set. Then the microcontroller must write the ad-

dress byte in the data register.

This bit is cleared by a read of the status register

(when SB is set), followed by a write in the data

disabled (PE=0) or by reset.

SR2F

ADD10

TRA

BUSY

BTF

ADSL

M/SL

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