ST7285C datasheet(42/117 Pages) STMICROELECTRONICS

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ST7285C

16-BIT TIMER (Cont’d)

4.3.5.2 Forced Compare Mode

The main purpose of the Forced Compare mode is

to facilitate fixed frequency generation.

In this section

i may represent 1 or 2.

When the Forced Output Level

i bit (FOLVi)of

TCR1 is written to 1, OLVL

i is copied to the OCMPi

pin. To provide this capability, internal logic allows

a single instruction to change OLVL

i and causes a

forced compare with the new value of OLVL

i.OCFi

is not affected, and thus no interrupt request is

generated.

4.3.5.3 One Pulse Mode

The One Pulse mode enables the generation of a

pulse on the occurence of an external event and is

programmed via the OPM bit in the TCR2 register.

The trigger event is applied to the Input Capture1

pin (ICAP1); the active edge of the event is flagged

by the IEDG1 bit in TCR1.

Then, on an event on ICAP1, the counter is initial-

ized to FFFCh and OLVL2 is loaded on the output

compare 1 pin (OCMP1); when the value of the

counter is equal to the value of the contents of

OCR1, the OLVL1 bit is output on the Output Com-

pare 1 pin (OCMP1). No interrupt is generated.

(See Figure 9).

4.3.5.4 Pulse Width Modulation Mode

This mode is similar to the One Pulse mode, in

which the external event is replaced by the Output

Compare 2 event; this mode is programmed via

the PWM bit in the TCR2 register.

OCR1 then contains the length of the pulse, while

OCR2 contains the value of the period; the Output

Compare 2 event causes the counter to be initial-

ized to FFFCh (See Figure 10). No interrupt is

generated

Figure 25. One Pulse Mode Timing, IEDG1=1; OCR1=2ED0h

Figure 26. Pulse Width Modulation Mode Timing, OCR1=2ED0h, OCR2=34E2

COUNTER

....

FFFC FFFD FFFE

2ED0

2ED1 2ED2

2ED3

FFF C FFFD

OLVL2

OLVL1

ICAP1

OCMP1

compare1

COUNTER

34E2

FFFC FFFD FFFE

2ED0 2ED1 2ED2

34E2

FFFC

OLVL2

OLVL1

OCMP1

compare2

compare1

compare2

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