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ST7285C

4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

4.1.1 Introduction

Each I/O Port can contain up to 8 individually pro-

grammable I/Os. The MCU features seven 8-bit

Ports (A, B, C,... G) and one 6-bit-port (H). Each I/

O pin is dedicated to its main functionality, thus re-

ducing and simplifying its programmability.

The current chapter describes the generic I/O

structure used in the MCU.

All I/Os are based on a generic circuit, of which a

block diagram is given in Figure 13. In most cases

the functions are simplified, and several sub-

blocks may be missing (such as, for instance, the

analog switch on ports B to H or pull-up and inter-

rupt logic for most of the I/O ports). Some registers

may also be absent where their functionality is re-

dundant: it is therefore advisable to consult the

Memory Map in section1.3 and the pin description

in section 1.2 for proper use of any particular I/O.

Only ports C4, C5, D4, D5, F0, F1, F2, F3, G3 fea-

ture interrupt capability.

The following sub-section 4.1.2 contains generic

information on ST7 I/O ports. For information spe-

cific to this device, please refer to sub-section

4.1.3.

4.1.2 Generic I/O Features

The I/O ports offer the following generic features:

– inputs with Schmitt trigger

– analog inputs, when connected via internal mul-

tiplexer

– interrupt generation, maskable by software

– EMI compliance thanks to reduced noise radia-

tion due to lowered cross-current in push pull

mode and reduced input susceptibility. This fea-

ture is particularly relevant in RDS applications.

Each

generic I/O pin may be individually program-

mable by software as:

– input: no pull-up, no interrupt generation

– input: pull-up, no interrupt generation

– input: pull-up, interrupt generation

– input: pull-down, no interrupt generation

– output: push-pull

– output: open-drain, no pull-up

– output: open-drain, with pull-up

4.1.2.1 Port Registers

Each port may be associated with up to four regis-

ters:

– DATA REGISTER (DR)

Address 0000 0000 000x xx00b; always present.

– DATA DIRECTION REGISTER(DDR)

Address 0000 0000 000x xx01b; always present.

– OPTION REGISTER (OR)

Address 0000 0000 000x xx10b; depending on

I/O dedication.

– PULL-UP REGISTER (PUR)

Address 0000 0000 000x xx11b; depending on

I/O dedication.

These are not internal CPU registers and must be

accessed by reading and writing to the relevant

memory locations. Refer toTable 1 - Memory Map

for the respective addresses and reset values.

4.1.2.2 Functional Description

Each I/O pin may be programmed independently

as an analog input if the port features analog capa-

bilities, as a digital input or a digital output with var-

ious variants, using the corresponding register

bits. When programmed as a digital input, a pull-up

or a pull-down resistor can, if present, be activated

by software. Only when enabling the pull-up, can

an interrupt function be programmed by software.

When programmed as an output, the I/O pin can

be programmed to operate either in push-pull or in

open-drain mode.

The interrupts generated by a port (active low) are

“ORed” to a single interrupt line that can be routed

to a CPU interrupt.

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