ST7285C datasheet(30/117 Pages) STMICROELECTRONICS

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ST7285C

SERIAL COMMUNICATIONS INTERFACE(Cont’d)

4.2.7.3 Control Register 2 (SCCR2)

Address: 0054h

—

Read/Write

Reset Value: 00h

Contains four control bits which allow interrupts

generated by TDR Empty, Transmit Complete,

RDR Full and Idle Line to be enabled or disabled.

Also contains four control bits to enable or disable

Transmission, Reception, Receiver Wake-Up and

Send Break.

Bit-7 = TIE Transmitter Interrupt Enable

Authorizes an interrupt when set at one and when

the TDRE (transmission register empty) flag is set

to “1” indicating that the last word has been trans-

mitted. When TIE is at zero this interrupt is disa-

bled.

Bit-6 = TCIE

Transmission Complete Interrupt En-

able

This bit set to “1” enables an interrupt when the TC

flag (transmission competed) changes to “1”.

When TCIE is at “0” this interrupt is disabled.

Bit-5 = RIE

Receiver Interrupt Enable

Authorizes an interrupt when set to “1” and when

either the RDRF (Receive Data Register Full) flag

or the OR (Overspeed on Reception) flag is set to

“1”, indicating that the last word has been transmit-

ted. When TIE is set to “0”, this interrupt is disa-

bled.

Bit-4 = ILIE

Idle Line Interrupt Enable

This bit at “1” enables an interrupt if the IDLE flag

changes to “1” (which corresponds to an idle line

on reception). The interrupt cannot occur if the

IDLE bit is at “0”.

Bit-3 = TE Transmitter Enable

This bit at “1” enables the transmitter. At start-up,

the transmitter sends a preamble (ten or eleven

ones). During transmission, a “0” pulse on the TE

bit (“0” followed by “1”) sends a preamble after the

current word. Setting the TE bit to “0” switches the

output line to a high impedance state at the end of

the word currently being transmitted.

Bit-2 = RE

Receiver Enable

The RE bit at “1” enables the receiver which be-

gins searching for a START bit. The RE bit at “0”

disables the receiver and resets the associated

status bits to “0” (RDRF, IDLE, OR, NF and FE).

Bit-1 = RWU

Receiver Wake-Up

The RWU bit at “1” mutes the receiver. The wake-

up mode is determined by the WAKE bit (bit 3 in

SCCR1). As long as RWU remains at “1”, the flags

relating to the receiver cannot rise to “1”.

Writing “0” to RWU forces an exit from the muted

state.

As soon as the wake-up sequence is recognized,

the RWU bit is forced to “0”. If the wake-up select-

ed mode corresponds to the reception of a pream-

ble, the RWU bit cannot be set to “1” as long as the

reception remains idle. If the selected wake-up

mode corresponds to the reception of a “1” on the

most significant bit, the reception of this particular

word wakes up the receiver and sets the RDRF

flag to “1”, which allows the receiver to receive this

word normally and to use it as an address word.

Bit-0 = SBK

Send Break

This bit set to “1” tells the transmitter to send a

whole number of BREAKS (all bits at “0” including

the stop bit). At the end of the last BREAK the

transmitter inserts an extra “1” bit in order to ac-

knowledge the START bit. If the SBK bit is set to

“1” and then to “0”, the transmitter will send a

BREAK word at the end of the current word.

4.2.7.4 Status Register (SCSR)

Address: 0050h

—

Read Only

Reset Value: 1100 0000b

Contains four flags which denote conditions which

can lead to interrupts if the corresponding bits of

SCCR2 are set: TDR Empty, Transmit Complete,

RDR Full and Idle Line. These flags are used for

management of the SCI interrupt system.

Also contains three flags which indicate error con-

ditions due to Overrun, Noise and Framing.

Bit-7 = TDRE Transmit Data Register Empty

Indicates that the content of the transmission data

If the TDRE bit is at “0”, it indicates that the trans-

mission has not yet occurred and that a write oper-

ation into the data register would overwrite previ-

ous data. The TDRE bit is reset to “0” by an SCSR

access followed by a write operation into the trans-

mission data register. Data will not be transferred

to the shift register as long as the TDRE bit is not

reset to “0”.

Bit-6 = TC Transmission Complete

543210

TIE

TCIE

RIE

ILIE

RWU

SBK

43210

TDRE

RDRF

IDLE

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