ST7285C datasheet(51/117 Pages) STMICROELECTRONICS

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ST7285C

SERIAL PERIPHERAL INTERFACE(Cont’d)

4.4.8 Serial Peripheral Status Register (SPSR)

Address: see Memory Map

—

Read Only

Reset Value: 00h

The status flags which generate a Serial Peripher-

al Interface (SPI) interrupt may be blocked by the

SPIE control bit in the Serial Peripheral Control

rupt. The Serial Peripheral Status register bits are

defined as follows:

Bit-7 = SPIF Serial Peripheral Data Transfer Flag

The Serial Peripheral Data Transfer Flag bit noti-

fies the user that a data transfer between the de-

vice and an external device has been completed.

With the completion of the data transfer, SPIF is

set, and if SPIE is set, a Serial Peripheral Interrupt

is generated. During the clock cycle SPIF is being

set, a copy of the received data byte in the shift

ter is read, it is the buffer that is read. In the event

of an overrun condition, when the Master device

has sent several bytes of data and the Slave de-

vice has not responded to the first SPIF, only the

first byte sent is contained in the receive buffer,

and all other bytes are lost.

Data transfer is initiated by the Master device writ-

ing to its Serial Peripheral Data I/O Register.

Clearing the SPIF bit is accomplished by a soft-

ware sequence which accesses the Serial Periph-

eral Status Register while SPIF is set, followed by

a write or read operation on the Serial Peripheral

Data I/O Register.

In the Master device, while SPIF is set, all writes to

the Serial Peripheral Data I/O Register are inhibit-

ed until the Serial Peripheral Status Register is

read.

In the Slave device, SPIF can be cleared (using a

similar sequence) during a second transmission;

however, it must be cleared before the second

SPIF bit in order to prevent an overrun condition.

The SPIF bit is cleared on Reset.

Bit-6 = WCOL Write Collision status bit

The Write Collision Status bit informs the user that

an attempt was made to write to the Serial Periph-

eral Data I/O Register while a data transfer was

taking place with an external device. The transfer

continues uninterrupted, and therefore a write will

be unsuccessful. A ”read collision” cannot occur,

since the received data byte is placed in a buffer in

which access is always synchronous with the

MCU operation. If a ”write collision” occurs, WCOL

is set but no SPI interrupt is generated. The WCOL

bit is a status flag only.

Clearing the WCOL bit is accomplished by a soft-

ware sequence of accessing the Serial Peripheral

Status Register while WCOL is set, followed by:

1) A read of the Serial Peripheral Data I/O Register

prior to the SPIF bit being set, or

2) A read or write of the Serial Peripheral Data I/O

A write to the Serial Peripheral Data I/O Register

(SPDR) prior to the SPIF bit being set, will result in

generation of another WCOL status flag. Both the

SPIF and WCOL bits will be cleared in the same

sequence. If a second transfer has started while

trying to clear the (previously set) SPIF and WCOL

bits with a clearing sequence comprising a write to

the Serial Peripheral Data I/O Register, only the

SPIF bit will be cleared.

A collision of a write to the Serial Peripheral Data

I/O Register while an external data transfer is tak-

ing place can occur both in the Master mode and

the Slave mode, although with proper program-

ming the Master device should have sufficient in-

formation to preclude this collision.

Collision in the Master device is defined as a write

of the Serial Peripheral Data I/O Register while the

internal rate clock (SCK) is in the process of trans-

fer. The signal on the SS pin is always at a logic

high level on the Master device.

Collision in a Slave device is defined in two sepa-

rate modes. A problem arises in a Slave device

when the CPHA control bit is reset. When CPHA is

reset, data is latched on the occurence of the first

clock transition. The Slave device does not have

any way of knowing when that transition will occur;

therefore, the Slave device collision occurs when it

attempts to write the Serial Peripheral Data I/O

CPHA bit is reset, the SS pin on the Slave device

freezes the data in its Serial Peripheral Data I/O

The Master device must raise the SS pin of the

Slave device to a logic high level between each

byte it transfers to the Slave device

SPIF

WCOL

MODF

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