ST7285C datasheet(48/117 Pages) STMICROELECTRONICS

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ST7285C

SERIAL PERIPHERAL INTERFACE(Cont’d)

4.4.6.1 Slave Select (SS)

The Slave select (SS) pin receives an active-low

signal which is generated by the Master device, in

order to enable Slave devices to accept data.

To ensure that data will be accepted by a Slave

device, the SS line must be at a logic lowlevel prior

to the occurence of SCK (system clock), and must

remain low until after the last (eighth) SCK cycle.

Figure 28 illustrates the relationship between SCK

and the data for two different level combinations of

CPHA, when SS is pulled low. These are :

– a) CPHA = 1 or 0, the first bit of data is applied

to the MISO line for transfer, and,

– b) when CPHA = 0 the Slave device is prevented

from writing to its data register. For further infor-

mation on the effect the SS input and the CPHA

have on the I/O data register, refer to the WCL

status flag in the ”Serial Peripheral Status Regis-

ter description”. A logic high level on theSS sig-

nal forces the MISO (Master In Slave Out) line to

the high-impedance state. Also, SCK and the

MOSI (Master Out Slave In) line are ignored by a

Slave device when its SS signal is at a logic high

level.

When a device is a Master, it constantly monitors

its SS signal input for the presence of a logic low

level. The Master device will become a Slave de-

vice any time its SS signal input is detected as be-

ing at a logic low level. This ensures that only one

Master controls theSS line.

When the SS line is detected as being at a logic

low level, the Master clears the MSTR control bit

(Serial Peripheral Control Register). Also, control

bit SPE in the Serial Peripheral Control Register is

cleared, causing the Serial Peripheral Interface

(SPI) to be disabled (SPI alternate function pins

become inputs). The MODF flag bit in the Serial

Peripheral Status Register is also set to indicate to

the Master device that another device is attempt-

ing to become a Master. Two devices attempting

to be outputs are normally the result of a software

error. However, the user system can be configured

in such manner as to contain a default Master

which would automatically ”take-over” and restart

the system.

4.4.6.2 Serial Clock (SCK)

The Serial Clock is used to synchronize the move-

ment of data both in and out of the device via its

MOSI and MISO pins. The Master and Slave de-

vices are capable of exchanging a data byte of in-

formation during a sequence of eight clock pulses.

Since the SCK is generated by the Master device,

the SCK line becomes an input on all Slave devic-

es and synchronizes Slave data transfer. The type

of clock and its relationship to data are controlled

by the CPOL and CPHA bits in the Serial Peripher-

al Control Register.

The Master device generates the SCK through a

circuit driven by the internal processor clock. Two

bits (SPR0 and SPR1) in the Serial Peripheral

Control Register of the Master device select the

clock rate. The Master device uses the SCK to

latch incoming Slave device data on the MISO line

and shifts out data to the Slave device on the

MOSI line. Both Master and Slave devices must

be operated in the same timing mode as defined

by the CPOL and CPHA bits in the Serial Peripher-

al Control Register.

In the Slave device, SPR0 and SPR1 have no ef-

fect on the operation of the Serial Peripheral Inter-

face.

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