ST7285C datasheet(19/117 Pages) STMICROELECTRONICS

19 / 117 page

19/117

ST7285C

3.4 WATCHDOG TIMER SYSTEM (WDG)

3.4.1 Introduction

The Watchdog timer is used to detect the oc-

curence of a software fault, usually generated by

external interference or by unforeseen logical con-

ditions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before it is decremented

to zero.

3.4.2 Functional Description

The counter is decremented every 12,288 ma-

chine cycles, and the length of the timeout period

can be programmed by the user in 64 increments,

ranging from 12,288 machine cycles to 786,432

machine cycles, depending on the value loaded in

bits 0-5 of the Watchdog register. The application

program must be written so that the Watchdog

mal operation.

The Watchdog is not activated automatically on

Reset, and must be activated by the user program

if required. Once activated it cannot be disabled,

save by a Reset.

During the Reset cycle, the device Reset pin acts

as an output that is pulsed low for 3 machine cy-

cles (6 oscillator cycles). In its high state, an inter-

nal pull-up resistor of about 100K

Ω is connected to

the Reset pin.

This resistor can be pulled low by external circuitry

to reset the device.

The Watchdog delay time is defined by bits 5-0 of

the Watchdog register; bit 6 must always be set in

order to avoid generating an immediate reset.

Conversely, this can be used to generate a soft-

ware reset (bit 7 = 1, bit 6 = 0).

Once bit 7 is set, it cannot be cleared by software:

i.e. the Watchdog cannot be disabled by software

without generating a Reset. The Watchdog timer

must be reloaded before bit 6 is decremented to ”0”

to avoid a Reset. Following a Reset, the Watchdog

If the Watchdog is activated, the HALT instruction

will generate a Reset.

If the circuit is not used as a Watchdog (i.e. bit 7 is

never set), bits 6 to 0 may be used as a simple 7-

bit timer, for instance as a real time clock. Since no

interrupt will be generated under these conditions,

the Watchdog register must be monitored by soft-

ware.

3.4.3 Watchdog Register

—

Read/ Write

Reset Value: 0111 1111 (7Fh)

b7 = WDGA: Activation bit (is active if set)

b6-0 =T6-T0: 7-bit timer counter (Msb to Lsb)

Table 4. Watchdog Timing (fOSC = 8 MHz)

WDGA

WDG Register initial

value

WDG timeout period (ms)

197

ST7285C Datenblatt(PDF) 19 Page - STMicroelectronics

ST7285C Datenblatt(HTML) 19 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL