ST7285C datasheet(37/117 Pages) STMICROELECTRONICS

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ST7285C

16-BIT TIMER (Cont’d)

When the counter rolls over from FFFFh to 0000h,

the Timer Overflow flag (TOF) of the Timer Status

erated if the TOIE enable bit of the Timer Control

CCR is cleared. If one of these conditions is false,

the interrupt remains pending to be issued as soon

as they are both true. The interrupt request is

cleared by reading TSR while TOF is set, followed

by an access (read or write) to the LSB of the

Counter Register.

The TOF flag is not affected by accesses to the Al-

ternate Counter Register. This feature allows si-

multaneous use of the overflow function and reads

of the free running counter at random times (for

example, to measure elapsed time) without risking

to clear the TOF flag erroneously. Accesses to the

timer without the intention of servicing the TOF

flag should therefore be performed to the Alternate

Counter Register while only the TOF service rou-

tine accesses the Counter Register.

The free running counter can be reset under soft-

ware control, by writing to the LSB of the Counter

counter and the prescaler are then configured to

their reset conditions. This reset also completes

any 16-bit access sequence. All flags and enable

bits are unchanged.

The value in the counter registers repeats every

131,072, 262,144, or 524,288 internal processor

clock cycles, depending on the clock control option

selected in TCR2. As shown in the timing dia-

grams, the counter increment is triggered by a fall-

ing edge of the CPU clock.

The timer is not affected by WAIT mode. In HALT

mode, the counter stops counting until the mode is

exited. Counting then resumes from the previous

count (MCU awakened by an interrupt) or from the

reset count (MCU awakened by a Reset).

4.3.3 External Clock

When the external clock is selected by setting the

relevant clock control bits in TCR2, the counter

clocks on each external clock rising edge, if

EXEDG in TCR2 is set, or the falling edges if reset,

and is synchronised with the falling edge of the in-

ternal CPU clock.

At least four falling edges of the CPU clock must

occur between two consecutive active edges of

the external clock; thus the external clock frequen-

cy must be less than a quarter of the CPU clock

frequency.

The parasitic pulses generated by the EXTEDG

and EXTCLKE transitions are filtered during two

clock periods, so the manipulation of the external

clock control bits must occur before or after two in-

ternal clock periods.

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