ST7285C datasheet(70/117 Pages) STMICROELECTRONICS

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ST7285C

RDS DEMODULATOR (Cont’d)

RDS DE1

Address 005C h

Reset Value: 0000 0000b

b7 = lock

Inhibits regulation of PLLs to keep the current

phase value during weak signal conditions.

0: normal regulation (Reset Value)

1: inhibit regulation.

b6-5 = lck3 - lck2

Select time constant for 1187.5Hz PLL.

b4-3 = lck1 - lck0

Select time constant of 57KHz PLL.

b2 = QEN

Enables automatic selection of input to differential

decoder 1.

0 = enable selection by quality (Reset Value)

1 = disable selection

b1 = SDAT

Selects differential decoder for the RDS data output.

0 = differential decoder 1 (Reset Value)

1 = differential decoder 2.

b0 = SQUAL

Selects quality for the quality output.

0 = from the quality detector (qal1) (Reset Value)

1 = exclusive OR of differential decoders (qal2).

RDS DE2

—

Address 005D h

Reset Value: 0xxx xxxx b

b7 = UPR

Software reset to various demodulator parts.

0 = normal run mode (Reset Value)

1 = demodulator reset.

After wring this bit to one, a reset pulse will be gen-

erated. The bit will then be automatically reset to

zero. This bit is always read as a zero.

b6 = QAL

Output of the quality detector which is actually de-

tected. This bit is fed into the RDS-GBS module.

b5 = QAL1

Output of the quality detector.

b4 = QAL2

Resulant of XOR of dat1 and dat2.

b3 = DAT

RDS-dat output which is actually detected. This bit

is fed into the RDS-GBS module.

b2 = DAT1

Output of the phase polarity data extractor.

b1 = DAT2

Output of the phase integral data extractor.

b0 = CLK

RDS clock output (1187.5Hz)

654321

lock

lck3

lck2

lck1

lck0

qen

sdat

squal

lck3

lck2

lock time needed for max (90

°)

deviation

160ms (Reset Value)

80ms

40ms

20ms

lck1

lck0

lock time needed for max (90

°)

deviation

16ms(Reset Value)

8ms

4ms

2ms

UPR

QAL

QAL1

QAL2

DAT

DAT1

DAT2

CLK

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