WM8994ECSSLASHR datasheet(105/363 Pages) CIRRUS

105 / 363 page

WM8994

Rev 4.6

105

DIGITAL TO ANALOGUE CONVERTER (DAC)

The WM8994 DACs receive digital input data from the DAC mixers -

see “Digital Mixing”. The digital

audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation

filters. The bitstream data enters four multi-bit, sigma-delta DACs, which convert them to high quality

analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and sensitivity to

clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion.

A high performance mode of DAC operation can be selected by setting the DAC_OSR128 bit - see

“Clocking and Sample Rates” for details.

The analogue outputs from the DACs can be mixed with analogue line/mic inputs using the line output

mixers MIXOUTL / MIXOUTR and the speaker output mixers SPKMIXL / SPKMIXR.

The DACs are enabled using the register bits defined in Table 47.

Note that the DAC clock must be enabled whenever the DACs are enabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5 (0005h)

Power

Management (5)

DAC2L_EN

Left DAC2 Enable

0 = Disabled

1 = Enabled

DAC2R_EN

Right DAC2 Enable

0 = Disabled

1 = Enabled

DAC1L_EN

Left DAC1 Enable

0 = Disabled

1 = Enabled

DAC1R_EN

Right DAC1 Enable

0 = Disabled

1 = Enabled

Table 47 DAC Enable Control

DAC CLOCKING CONTROL

Clocking for the DACs is derived from SYSCLK. The required clock is enabled when the

SYSDSPCLK_ENA register is set.

The DAC clock rate is configured automatically, according to the AIFn_SR, AIFnCLK_RATE and

DAC_OSR128 registers. (See “Clocking and Sample Rates” for further details of the system clocks

and control registers.)

When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the DAC clocking is

controlled by the AIF1_SR and AIF1CLK_RATE registers.

When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then the DAC clocking is

controlled by the AIF2_SR and AIF2CLK_RATE registers.

The supported DAC clocking configurations are described in Table 48 (for DAC_OSR128=0) and

Table 49 (for DAC_OSR128=1). Under default conditions, the DAC_OSR128 bit is not set.

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