WM8994ECSSLASHR datasheet(106/363 Pages) CIRRUS

106 / 363 page

WM8994

106

Rev 4.6

SAMPLE

RATE (kHz)

SYSCLK RATE (AIFnCLK / fs ratio)

128

192

256

384

512

768

1024

1536



11.025

Note 1



Note 1



Note 1



22.05

Note 1



Note 1



Note 1



44.1

Note 1



Note 1



88.2

Note 1

When DAC_OSR128=0, DAC operation is only supported for the configurations indicated above

Table 48 DAC Clocking - DAC_OSR128 = 0 (Default)

SAMPLE

RATE (kHz)

SYSCLK RATE (AIFnCLK / fs ratio)

128

192

256

384

512

768

1024

1536



11.025



22.05

Note 1



Note 1



Note 1



44.1

Note 1



Note 1



88.2

Note 1

When DAC_OSR128=1, DAC operation is only supported for the configurations indicated above

Table 49 DAC Clocking - DAC_OSR128 = 1

Note 1 - These clocking rates are only supported

for ‘simple’ DAC-only playback modes, under the

following conditions:



AIF input is enabled on a single interface (AIF1 or AIF2) only, or is enabled on AIF1 and

AIF2 simultaneously provided AIF1 and AIF2 are synchronised (ie. AIF1CLK_SRC =

AIF2CLK_SRC)



All AIF output paths are disabled



All DSP functions (ReTune Mobile Parametric Equaliser, 3D stereo expansion and Dynamic

Range Control) are disabled

The clocking requirements in Table 48 and Table 49 are only applicable to the AIFnCLK that is

selected as the SYSCLK source. Note that both clocks (AIF1CLK and AIF2CLK) must satisfy the

requirements noted in the “Clocking and Sample Rates” section.

The applicable clocks (SYSCLK, and AIF1CLK or AIF2CLK) must be present and enabled when using

the Digital to Analogue Converters (DACs).

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