MSP432P411VIPZ datasheet(29/212 Pages) TI1

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MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

www.ti.com

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Terminal Configuration and Functions

Table 4-3. Signal Descriptions (continued)

FUNCTION

SIGNAL NAME

SIGNAL NO. (1)

SIGNAL

TYPE (2)

DESCRIPTION

RGC

Timer

PM_TA1.1

N/A

I/O

Default mapping: TA1 CCR1 capture: CCI1A input,

compare: Out1

TA1.0

I/O

TA1 CCR0 capture: CCI0A input, compare: Out0

TA2.0

I/O

TA2 CCR0 capture: CCI0A input, compare: Out0

TA2.1

I/O

TA2 CCR1 capture: CCI1A input, compare: Out1

TA2.2

I/O

TA2 CCR2 capture: CCI2A input, compare: Out2

TA2.3

I/O

TA2 CCR3 capture: CCI3A input, compare: Out3

TA2.4

I/O

TA2 CCR4 capture: CCI4A input, compare: Out4

TA2CLK

TA2 input clock

TA3.0

N/A

I/O

TA3 CCR0 capture: CCI0A input, compare: Out0

TA3.1

N/A

I/O

TA3 CCR1 capture: CCI1A input, compare: Out1

TA3.2

N/A

I/O

TA3 CCR2 capture: CCI2A input, compare: Out2

TA3.3

N/A

I/O

TA3 CCR3 capture: CCI3A input, compare: Out3

TA3.4

N/A

I/O

TA3 CCR4 capture: CCI4A input, compare: Out4

TA3CLK

N/A

TA3 input clock

UART

UCA0RXD

Receive data for eUSCI_A0 UART mode

UCA0TXD

Transmit data for eUSCI_A0 UART mode

UCA3RXD

N/A

Receive data for eUSCI_A3 UART mode

UCA3TXD

N/A

Transmit data for eUSCI_A3 UART mode

(1)

This is a switch, not a buffer.

(2)

Only for input pins.

(3)

This is supply input, not a buffer.

4.5

Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for

example, if the device is in test mode). For details of the settings for each pin and diagrams of the

multiplexed ports, see Section 6.12.

4.6

Buffer Types

Table 4-4 describes the buffer types that are referenced in Table 4-1 and Table 4-2.

Table 4-4. Buffer Type

BUFFER TYPE

(STANDARD)

NOMINAL

VOLTAGE

HYSTERESIS

PU OR PD

NOMINAL PU OR

PD STRENGTH

(µA)

OUTPUT DRIVE

STRENGTH (mA)

OTHER

CHARACTERISTIC

Analog (1)

3.0 V

N/A

See analog modules

in Section 5 for

details.

HVCMOS

13.0 V

N/A

See Section 5.26.6.

LVCMOS

3.0 V

Y (2)

Programmable

See Section 5.26.6.

Power (DVCC) (3)

3.0 V

N/A

SVSMH enables

hysteresis on

DVCC.

Power (AVCC) (3)

3.0 V

N/A

Power (DVSS and

AVSS) (3)

0 V

N/A

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