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MSP432P411VIPZ Datenblatt(PDF) 70 Page - Texas Instruments |
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MSP432P411VIPZ Datenblatt(HTML) 70 Page - Texas Instruments |
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70 / 212 page ![]() 70 MSP432P4111, MSP432P4011, MSP432P411Y MSP432P401Y, MSP432P411V, MSP432P401V SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com Submit Documentation Feedback Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V Specifications Copyright © 2017–2018, Texas Instruments Incorporated Table 5-28 lists the timing parameters of the ADC. (1) MODOSC can be used for 1 Msps and SYSOSC can be used for 200 ksps sampling rate operations of ADC. (2) The condition is that the error in a conversion started after tADC14ON is less than ±1 LSB. The reference and input signal are already settled. (3) Sampling time should be at least 4 × (1 / fADC14CLK). (4) tsample ≥ (n + 1) × ln(2) × [(RS + RI) × CI + RS × (Cpext + Cpint)], where n = ADC resolution =14, RS = external source resistance, Cpext = external parasitic capacitance. Table 5-28. Precision ADC Timing Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fADC14CLK ADC clock frequency(1) ADC14PWRMD = 0 1.8 V to 3.7 V 0.128 25 MHz ADC14PWRMD = 2 1.62 V to 3.7 V 0.128 5.75 NCONVERT Clock cycles for conversion ADC14RES = 11 16 cycles ADC14RES = 10 14 ADC14RES = 01 11 ADC14RES = 00 9 tADC14ON Turnon settling time of ADC See (2) 1.5 µs tSample Sampling time(3) (4) RS = 200 Ω, Cpext = 10 pF, RI = 1 kΩ, CI = 15 pF, Cpint = 5 pF 0.215 µs Table 5-29 lists the linearity parameters of the ADC. (1) Minimum reference voltage of 1.45 V is necessary to meet the specified accuracy. Lower reference voltage down to 1.2 V can be applied for 1-Msps sampling rate with reduced accuracy requirements. (2) Connect the VeREF- pin to onboard ground for ADC14VRSEL = 0xE. Table 5-29. Precision ADC Linearity Parameters(1)(2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 14 bits EI Integral linearity error (INL) ±2.3 LSB ED Differential linearity error (DNL) –0.99 1 LSB EO Offset error ADC14VRSEL = 0xE, 0xF ±0.2 ±1 mV ADC14VRSEL = 0x1 ±1.2 ±2 EG Gain error ADC14VRSEL = 0xE ±2 ±4 LSB ADC14VRSEL = 0xF ±20 ±60 ADC14VRSEL = 0x1 ±50 ±180 ET Total unadjusted error ADC14VRSEL = 0xE ±4 ±15 LSB ADC14VRSEL = 0xF ±22 ±62 ADC14VRSEL = 0x1 ±55 ±185 |
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