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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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MSP432P411VIPZ Datenblatt(PDF) 48 Page - Texas Instruments |
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MSP432P411VIPZ Datenblatt(HTML) 48 Page - Texas Instruments |
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48 / 212 page  48 MSP432P4111, MSP432P4011, MSP432P411Y MSP432P401Y, MSP432P411V, MSP432P401V SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com Submit Documentation Feedback Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V Specifications Copyright © 2017–2018, Texas Instruments Incorporated Table 5-5 lists the latencies required to change between different active and LPM0 modes. (1) This is the latency between execution of WFI instruction by CPU to assertion of SLEEPING signal at CPU output. (2) This is the latency between I/O interrupt event to deassertion of SLEEPING signal at CPU output. Table 5-5. LPM0 Mode Transition Latencies over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ORIGINAL OPERATING MODE FINAL OPERATING MODE TEST CONDITIONS TYP MAX UNIT tAMLDOx_LPM0LDOx (1) AM_LDO_VCOREx LPM0_LDO_VCOREx Transition from AM_LDO_VCORE0 or AM_LDO_VCORE1 to LPM0_LDO_VCORE0 or LPM0_LDO_VCORE1 1 MCLK cycles tLPM0LDOx_AMLDOx (2) LPM0_LDO_VCOREx AM_LDO_VCOREx Transition from LPM0_LDO_VCORE0 or LPM0_LDO_VCORE1 to AM_LDO_VCORE0 or AM_LDO_VCORE1 through I/O interrupt 3 4 MCLK cycles tAMDCDCx_LPM0DCDCx (1) AM_DCDC_VCOREx LPM0_DCDC_VCOREx Transition from AM_DCDC_VCORE0 or AM_DCDC_VCORE1 to LPM0_DCDC_VCORE0 or LPM0_DCDC_VCORE1 1 MCLK cycles tLPM0DCDCx_AMDCDCx (2) LPM0_DCDC_VCOREx AM_DCDC_VCOREx Transition from LPM0_DCDC_VCORE0 or LPM0_DCDC_VCORE1 to AM_DCDC_VCORE0 or AM_DCDC_VCORE1 through I/O interrupt 3 4 MCLK cycles tAMLFx_LPM0LFx (1) AM_LF_VCOREx LPM0_LF_VCOREx Transition from AM_LF_VCORE0 or AM_LF_VCORE1 to LPM0_LF_VCORE0 or LPM0_LF_VCORE1 1 MCLK cycles tLPM0LFx_AMLFx (2) LPM0_LF_VCOREx AM_LF_VCOREx Transition from LPM0_LF_VCORE0 or LPM0_LF_VCORE1 to AM_LF_VCORE0 or AM_LF_VCORE1 through I/O interrupt 3 4 MCLK cycles |
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