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MSP432P411VIPZ Datenblatt(PDF) 35 Page - Texas Instruments

Teilenummer MSP432P411VIPZ
Bauteilbeschribung  SimpleLink Mixed-Signal Microcontrollers
PDF  212 Pages
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

MSP432P411VIPZ Datenblatt(HTML) 35 Page - Texas Instruments

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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
(1)
Device held in reset through RSTn/NMI pin.
(2)
Current measured into VCC.
(3)
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
5.9
Current Consumption During Device Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1) (2) (3)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
IRESET
Current during device reset
2.2 V
690
µA
3.0 V
760
1000
(1)
MCLK sourced by DCO.
(2)
Current measured into VCC.
(3)
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
(4)
All SRAM banks are active.
(5)
All peripherals are inactive.
(6)
Device executing the Dhrystone 2.1 program. Code execution from flash, stack, and data in SRAM.
(7)
Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
(8)
Flash instruction and data buffers are enabled (BUFI = BUFD = 1).
(9)
Device executing the Dhrystone 2.1 program. Code execution from SRAM, stack and data in SRAM.
5.10 Current Consumption in LDO-Based Active Modes – Dhrystone 2.1 Program
over recommended operating free-air temperature (unless otherwise noted)
(1) (2) (3) (4) (5)
PARAMETER
EXECUTION
MEMORY
VCC
MCLK = 1 MHz
MCLK = 8 MHz
MCLK =
16 MHz
MCLK =
24 MHz
MCLK =
32 MHz
MCLK =
40 MHz
MCLK =
48 MHz
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
IAM_LDO_VCORE0,Flash
(6) (7) (8)
Flash
3.0 V
700
950
2000
2400
3200
3600
4000
4500
µA
IAM_LDO_VCORE1,Flash
(6) (7) (8)
Flash
3.0 V
720
1050
2150
2600
3520
4000
5000
5600
5700
6300
7000
7600
7300
8200
µA
IAM_LDO_VCORE0,SRAM
(9)
SRAM
3.0 V
640
900
1600
2000
2675
3100
3750
4250
µA
IAM_LDO_VCORE1,SRAM
(9)
SRAM
3.0 V
650
1000
1625
2100
2725
3200
3825
4350
5000
5550
6100
6800
7200
7900
µA
(1)
MCLK sourced by DCO.
(2)
Current measured into VCC.
(3)
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
(4)
All SRAM banks are active.
(5)
All peripherals are inactive.
(6)
Device executing the Dhrystone 2.1 program. Code execution from flash. Stack and data in SRAM.
(7)
Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
(8)
Flash instruction and data buffers are enabled (BUFI = BUFD = 1).
(9)
Device executing the Dhrystone 2.1 program. Code execution from SRAM. Stack and data in SRAM.
5.11 Current Consumption in DC/DC-Based Active Modes – Dhrystone 2.1 Program
over recommended operating free-air temperature (unless otherwise noted)
(1) (2) (3) (4) (5)
PARAMETER
EXECUTION
MEMORY
VCC
MCLK = 1 MHz
MCLK = 8 MHz
MCLK =
16 MHz
MCLK =
24 MHz
MCLK =
32 MHz
MCLK =
40 MHz
MCLK =
48 MHz
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
IAM_DCDC_VCORE0,Flash
(6) (7) (8)
Flash
3.0 V
580
800
1280
1750
1970
2300
2390
2900
µA
IAM_DCDC_VCORE1,Flash
(6) (7) (8)
Flash
3.0 V
620
900
1490
1850
2325
2750
3250
3800
3650
4250
4450
5100
4650
5300
µA
IAM_DCDC_VCORE0,SRAM
(9)
SRAM
3.0 V
550
750
1040
1400
1600
2000
2170
2650
µA
IAM_DCDC_VCORE1,SRAM
(9)
SRAM
3.0 V
580
850
1150
1550
1790
2200
2440
2900
3100
3650
3770
4400
4400
5100
µA



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