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MSP432P411VIPZ Datenblatt(PDF) 36 Page - Texas Instruments |
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MSP432P411VIPZ Datenblatt(HTML) 36 Page - Texas Instruments |
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36 / 212 page ![]() 36 MSP432P4111, MSP432P4011, MSP432P411Y MSP432P401Y, MSP432P411V, MSP432P401V SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com Submit Documentation Feedback Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V Specifications Copyright © 2017–2018, Texas Instruments Incorporated (1) Current measured into VCC. (2) All other input pins tied to 0 V or VCC. Outputs do not source or sync any current. (3) MCLK sourced by REFO at 128 kHz. (4) All peripherals are inactive. (5) SRAM banks 0 and 1 enabled for execution from flash, and SRAM banks 0 to 3 enabled for execution from SRAM. (6) Flash configured to 0 wait states. (7) Device executing the Dhrystone 2.1 program. Code execution from Flash. Stack and data in SRAM. (8) Flash instruction and data buffers are enabled (BUFI = BUFD = 1). (9) Device executing the Dhrystone 2.1 program. Code execution from SRAM. Stack and data also in SRAM. 5.12 Current Consumption in Low-Frequency Active Modes – Dhrystone 2.1 Program over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) (3) (4) (5) PARAMETER EXECUTION MEMORY VCC –40°C 25°C 60°C 85°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX IAM_LF_VCORE0, flash (6) (7) (8) Flash 2.2 V 90 95 110 140 μA 3.0 V 90 95 120 110 150 350 IAM_LF_VCORE1, flash (6) (7) (8) Flash 2.2 V 92 100 120 160 μA 3.0 V 95 110 150 130 200 500 IAM_LF_VCORE0, SRAM (9) SRAM 2.2 V 88 95 110 140 μA 3.0 V 88 95 115 110 150 300 IAM_LF_VCORE1, SRAM (9) SRAM 2.2 V 92 98 118 165 μA 3.0 V 93 100 130 120 166 400 |
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