MSP432P411VIPZ datasheet(87/212 Pages) TI1

87 / 212 page

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Specifications

5.26.11 eUSCI

Table 5-39 lists the supported clock frequencies of the eUSCI in UART mode.

Table 5-39. eUSCI (UART Mode) Clock Frequency

PARAMETER

TEST CONDITIONS

VCORE

VCC

MIN

MAX

UNIT

feUSCI

eUSCI input clock frequency

Internal: SMCLK,

External: UCLK,

Duty cycle = 50% ±10%

1.2 V

MHz

1.4 V

fBITCLK

BITCLK clock frequency

(equals baud rate in MBaud)

1.2 V

MHz

1.4 V

Table 5-40 lists the characteristics of the eUSCI in UART mode.

(1)

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch

time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration must exceed the maximum

specification of the deglitch time.

Table 5-40. eUSCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

UART receive deglitch time(1)

UCGLITx = 0

UCGLITx = 1

UCGLITx = 2

100

UCGLITx = 3

150

Table 5-41 lists the supported clock frequencies of the eUSCI in SPI master mode.

Table 5-41. eUSCI (SPI Master Mode) Clock Frequency

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

feUSCI

eUSCI input clock frequency

SMCLK

Duty cycle = 50% ±10%

VCORE = 1.2 V

MHz

VCORE = 1.4 V

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