MSP432P411VIPZ datasheet(9/212 Pages) TI1

9 / 212 page

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

www.ti.com

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Terminal Configuration and Functions

(1)

(RD) indicates the reset default signal name for that pin.

(2)

To determine the pin mux encodings for each pin, see Section 6.12.

(3)

Signal Types: I = Input, O = Output, I/O = Input or Output, P = power

(4)

Buffer Types: See Section 4.6 for details

(5)

The power source shown in this table is the I/O power source, which may differ from the module power source.

(6)

Reset States:

OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled

PD = High-impedance input with pulldown enabled

PU = High-impedance input with pullup enabled

N/A = Not applicable

(7)

This LCD drive pin is also mirrored at a different location in the 100-pin PZ package. Assign the LCD drive output to only one pin at a

time.

4.3

Pin Attributes

Table 4-1 describes the attributes of the pins for the MSP432P411xI devices.

Table 4-1. Pin Attributes for MSP432P411xI

PIN NO.

(PZ

PACKAGE)

SIGNAL NAME (1) (2)

SIGNAL TYPE (3)

BUFFER TYPE (4)

POWER SOURCE

(5)

RESET STATE

AFTER POR (6)

P10.1 (RD)

I/O

LVCMOS

DVCC

OFF

UCB3CLK

I/O

LVCMOS

DVCC

N/A

L38

Analog

DVCC

N/A

P10.2 (RD)

I/O

LVCMOS

DVCC

OFF

UCB3SIMO

I/O

LVCMOS

DVCC

N/A

UCB3SDA

I/O

LVCMOS

DVCC

N/A

L37

Analog

DVCC

N/A

P10.3 (RD)

I/O

LVCMOS

DVCC

OFF

UCB3SOMI

I/O

LVCMOS

DVCC

N/A

UCB3SCL

I/O

LVCMOS

DVCC

N/A

L36

Analog

DVCC

N/A

P1.0 (RD)

I/O

LVCMOS

DVCC

OFF

UCA0STE

I/O

LVCMOS

DVCC

N/A

L19 (7)

Analog

DVCC

N/A

P1.1 (RD)

I/O

LVCMOS

DVCC

OFF

UCA0CLK

I/O

LVCMOS

DVCC

N/A

L18 (7)

Analog

DVCC

N/A

P1.2 (RD)

I/O

LVCMOS

DVCC

OFF

UCA0RXD

LVCMOS

DVCC

N/A

UCA0SOMI

I/O

LVCMOS

DVCC

N/A

L17 (7)

Analog

DVCC

N/A

P1.3 (RD)

I/O

LVCMOS

DVCC

OFF

UCA0TXD

LVCMOS

DVCC

N/A

UCA0SIMO

I/O

LVCMOS

DVCC

N/A

L16 (7)

Analog

DVCC

N/A

P1.4 (RD)

I/O

LVCMOS

DVCC

OFF

UCB0STE

I/O

LVCMOS

DVCC

N/A

L15 (7)

Analog

DVCC

N/A

P1.5 (RD)

I/O

LVCMOS

DVCC

OFF

UCB0CLK

I/O

LVCMOS

DVCC

N/A

L14 (7)

Analog

DVCC

N/A

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