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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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MSP432P411VIPZ Datenblatt(PDF) 92 Page - Texas Instruments |
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MSP432P411VIPZ Datenblatt(HTML) 92 Page - Texas Instruments |
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92 / 212 page  SDA SCL t HD,DAT t SU,DAT t HD,STA t HIGH t LOW t BUF t HD,STA t SU,STA t SP t SU,STO 92 MSP432P4111, MSP432P4011, MSP432P411Y MSP432P401Y, MSP432P411V, MSP432P401V SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com Submit Documentation Feedback Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V Specifications Copyright © 2017–2018, Texas Instruments Incorporated Table 5-44 lists the supported clock frequencies of the eUSCI in I2C mode. Table 5-44. eUSCI (I2C Mode) Clock Frequency PARAMETER TEST CONDITIONS VCORE VCC MIN MAX UNIT feUSCI eUSCI input clock frequency Internal: SMCLK, External: UCLK, Duty cycle = 50% ±10% 1.2 V 12 MHz 1.4 V 24 fSCL SCL clock frequency 1 MHz Table 5-45 lists the characteristics of the eUSCI in I2C mode. Table 5-45. eUSCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-73) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tHD,STA Hold time (repeated) START fSCL = 100 kHz 5.5 µs fSCL = 400 kHz 1.5 fSCL = 1 MHz 0.6 tSU,STA Setup time for a repeated START fSCL = 100 kHz 5.5 µs fSCL = 400 kHz 1.5 fSCL = 1 MHz 0.6 tHD,DAT Data hold time fSCL = 100 kHz 80 ns fSCL = 400 kHz 80 fSCL = 1 MHz 80 tSU,DAT Data setup time fSCL = 100 kHz 5.5 µs fSCL = 400 kHz 1.5 fSCL = 1 MHz 0.6 tSU,STO Setup time for STOP fSCL = 100 kHz 5.5 µs fSCL = 400 kHz 1.5 fSCL = 1 MHz 0.6 tSP Pulse duration of spikes suppressed by input filter UCGLITx = 0 50 120 ns UCGLITx = 1 25 60 UCGLITx = 2 10 35 UCGLITx = 3 5 20 tTIMEOUT Clock low time-out UCCLTOx = 1 27 ms UCCLTOx = 2 30 UCCLTOx = 3 33 Figure 5-73. I2C Mode Timing |
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