MSP432P411VIPZ datasheet(63/212 Pages) TI1

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MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Specifications

5.26.6 Digital I/Os

Table 5-23 lists the characteristics of the digital inputs.

(1)

The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.

(2)

The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

(3)

An external signal sets the interrupt flag every time the minimum interrupt pulse duration tint is met. It may be set by trigger signals

shorter than tint.

(4)

A trigger pulse duration less than the MIN value is always filtered, and a trigger pulse duration more than the MAX value is always

passed. The trigger pulse may or may not be filtered if the duration is between the MIN and MAX values.

(5)

Not applicable if RSTn/NMI pin configured as NMI.

Table 5-23. Digital Inputs (Applies to Both Normal and High-Drive I/Os)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

VIT+

Positive-going input threshold voltage

2.2 V

0.99

1.65

3 V

1.35

2.25

VIT–

Negative-going input threshold voltage

2.2 V

0.55

1.21

3 V

0.75

1.65

Vhys

Input voltage hysteresis (VIT+ – VIT–)

2.2 V

0.32

0.84

3 V

0.4

1.0

RPull

Pullup or pulldown resistor

For pullup: VIN = VSS,

For pulldown: VIN = VCC

kΩ

CI,dig

Input capacitance, digital only port pins

VIN = VSS or VCC

CI,ana

Input capacitance, port pins shared with

analog functions

VIN = VSS or VCC

Ilkg,ndio

Normal I/O high-impedance input leakage

current

See (1)(2)

2.2 V, 3 V

±20

Ilkg,hdio

High-drive I/O high-impedance input leakage

current

See (1)(2)

2.2 V, 3 V

±20

tint

External interrupt timing (external trigger

pulse duration to set interrupt flag)

Ports with interrupt capability and

without glitch filter (3)

2.2 V, 3 V

Ports with interrupt capability and

with glitch filter, glitch filter disabled

(GLTFLT_EN = 0) (3)

2.2 V, 3 V

Ports with interrupt capability and

with glitch filter, glitch filter enabled

(GLTFTL_EN = 1) (4)

2.2 V, 3 V

0.25

µs

tRST

External reset pulse duration on RSTn pin(5)

2.2 V, 3 V

µs

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