MSP432P411VIPZ datasheet(30/212 Pages) TI1

30 / 212 page

MSP432P4111, MSP432P4011, MSP432P411Y

MSP432P401Y, MSP432P411V, MSP432P401V

SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018

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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V

Terminal Configuration and Functions

(1)

For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.

4.7

Connections for Unused Pins

Table 4-5 lists the correct termination of all unused pins.

Table 4-5. Connection for Unused Pins (1)

POTENTIAL

COMMENT

AVCC

DVCC

AVSS

DVSS

VSW

Open

Leave VSW pin unconnected if DC/DC regulator operation is not required.

Px.0 to Px.7

Open

Set to port function, output direction, and leave unconnected on the PCB.

RSTn/NMI

DVCC or VCC

47-kΩ pullup with 1.1-nF pulldown

PJ.4/TDI

Open

The JTAG TDI pin is shared with general-purpose I/O function (PJ.4). If not being used,

set this pin to port function, output direction. When used as the JTAG TDI pin, leave this

pin open.

PJ.5/TDO/SWO

DVCC or VCC

The JTAG TDO/SWO pin is shared with general-purpose I/O function (PJ.5). If not being

used, set this pin to port function, output direction. When used as the JTAG TDO/SWO

pin, use an external pulldown on this pin.

SWDIOTMS

DVCC or VCC

Use an external pullup on this pin.

SWCLKTCK

DVCC or VCC

Use an external pulldown on this pin.

MSP432P411VIPZ Datenblatt(PDF) 30 Page - Texas Instruments

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