WM8994ECSSLASHR datasheet(116/363 Pages) CIRRUS

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WM8994

116

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1 (0001h)

Power

Management

(1)

HPOUT1L_ENA

Enables HPOUT1L input stage

0 = Disabled

1 = Enabled

For normal operation, this bit should

be set as the first step of the

HPOUT1L Enable sequence.

HPOUT1R_ENA

Enables HPOUT1R input stage

0 = Disabled

1 = Enabled

For normal operation, this bit should

be set as the first step of the

HPOUT1R Enable sequence.

R96 (0060h)

Analogue HP

(1)

HPOUT1L_RMV_

SHORT

Removes HPOUT1L short

0 = HPOUT1L short enabled

1 = HPOUT1L short removed

For normal operation, this bit should

be set as the final step of the

HPOUT1L Enable sequence.

HPOUT1L_OUTP

Enables HPOUT1L output stage

0 = Disabled

1 = Enabled

For normal operation, this bit should

be set to 1 after the DC offset

cancellation has been scheduled.

HPOUT1L_DLY

Enables HPOUT1L intermediate stage

0 = Disabled

1 = Enabled

For normal operation, this bit should

be set to 1 after the output signal path

has been configured, and before DC

offset cancellation is scheduled. This

bit should be set with at least 20us

delay after HPOUT1L_ENA.

HPOUT1R_RMV_

SHORT

Removes HPOUT1R short

0 = HPOUT1R short enabled

1 = HPOUT1R short removed

For normal operation, this bit should

be set as the final step of the

HPOUT1R Enable sequence.

HPOUT1R_OUTP

Enables HPOUT1R output stage

0 = Disabled

1 = Enabled

For normal operation, this bit should

be set to 1 after the DC offset

cancellation has been scheduled.

HPOUT1R_DLY

Enables HPOUT1R intermediate stage

0 = Disabled

1 = Enabled

For normal operation, this bit should

be set to 1 after the output signal path

has been configured, and before DC

offset cancellation is scheduled. This

bit should be set with at least 20us

delay after HPOUT1R_ENA.

Table 56 Headphone Output Signal Paths Control

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