WM8994ECSSLASHR datasheet(137/363 Pages) CIRRUS

137 / 363 page

WM8994

Rev 4.6

137

where appropriate, to ensure there is no active audio signal present during the DC Servo

measurements.

Writing a logic 1 to DCS_TRIG_DAC_WR_n causes the DC offset correction to be set to the value

contained in the DCS_DAC_WR_VAL_n fields in Register R89. This mode is useful if the required

offset

correction

has

already

been

determined

and

stored;

faster

than

the

DCS_TRIG_STARTUP_n mode, but relies on the accuracy of the stored settings. Completion of the

DC offset correction triggered in this way is indicated by the DCS_DAC_WR_COMPLETE field, as

described in Table 71. Typically, this operation takes 2ms per channel.

For pop-free operation of the DC Servo DAC Write mode, it is important that the mode is scheduled at

the correct position within the Headphone Output Enable sequence, as described in the

“Analogue

Output Signal Path

” section.

The current DC offset value for each Headphone output channel can be read from the

DCS_DAC_WR_VAL_n fields. These values may form the basis of settings that are subsequently

used by the DC Servo in DAC Write mode. Note that these fields have a different definition for Read

and Write, as described in Table 71.

When using either of the DC Servo options above, the status of the DC offset correction process is

indicated

the

DCS_CAL_COMPLETE

field;

this

the

logical

the

DCS_STARTUP_COMPLETE and DCS_DAC_WR_COMPLETE fields.

The DCS_DAC_WR_COMPLETE bits can be used as inputs to the Interrupt control circuit or used to

generate an external logic signal on a GPIO pin. See “Interrupts” and “General Purpose Input/Output”

for further details.

The DC Servo control fields associated with start-up operation are described in Table 71. It is

important to note that, to minimise audible pops/clicks, the Start-Up and DAC Write modes of DC

Servo operation should be commanded as part of a control sequence which includes muting and

shorting of the headphone outputs; a suitable sequence is defined in the default Start-Up sequence.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R84 (0054h)

DC Servo (1)

DCS_TRIG_START

UP_1

Writing 1 to this bit selects Start-

Up DC Servo mode for

HPOUT1R.

In readback, a value of 1

indicates that the DC Servo

Start-Up correction is in

progress.

DCS_TRIG_START

UP_0

Writing 1 to this bit selects Start-

Up DC Servo mode for

HPOUT1L.

In readback, a value of 1

indicates that the DC Servo

Start-Up correction is in

progress.

DCS_TRIG_DAC_W

R_1

Writing 1 to this bit selects DAC

Write DC Servo mode for

HPOUT1R.

In readback, a value of 1

indicates that the DC Servo DAC

Write correction is in progress.

DCS_TRIG_DAC_W

R_0

Writing 1 to this bit selects DAC

Write DC Servo mode for

HPOUT1L.

In readback, a value of 1

indicates that the DC Servo DAC

Write correction is in progress.

DCS_ENA_CHAN_1

DC Servo enable for HPOUT1R

0 = Disabled

1 = Enabled

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