WM8994ECSSLASHR datasheet(138/363 Pages) CIRRUS

138 / 363 page

WM8994

138

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DCS_ENA_CHAN_0

DC Servo enable for HPOUT1L

0 = Disabled

1 = Enabled

R88 (0058h)

DC Servo

Readback

9:8

DCS_CAL_COMPL

ETE [1:0]

DC Servo Complete status

0 = DAC Write or Start-Up DC

Servo mode not completed.

1 = DAC Write or Start-Up DC

Servo mode complete.

Bit [1] = HPOUT1R

Bit [0] = HPOUT1L

5:4

DCS_DAC_WR_CO

MPLETE [1:0]

DC Servo DAC Write status

0 = DAC Write DC Servo mode

not completed.

1 = DAC Write DC Servo mode

complete.

Bit [1] = HPOUT1R

Bit [0] = HPOUT1L

1:0

DCS_STARTUP_C

OMPLETE [1:0]

DC Servo Start-Up status

0 = Start-Up DC Servo mode not

completed.

1 = Start-Up DC Servo mode

complete.

Bit [1] = HPOUT1R

Bit [0] = HPOUT1L

R89 (0059h)

DC Servo

Write Val

15:8

DCS_DAC_WR_VA

L_1 [7:0]

00h

Writing to this field sets the DC

Offset value for HPOUT1R in

DAC Write DC Servo mode.

Reading this field gives the

current DC Offset value for

HPOUT1R.

Two’s complement format.

LSB is 0.25mV.

Range is -32mV to +31.75mV

7:0

DCS_DAC_WR_VA

L_0 [7:0]

00h

Writing to this field sets the DC

Offset value for HPOUT1L in

DAC Write DC Servo mode.

Reading this field gives the

current DC Offset value for

HPOUT1L.

Two’s complement format.

LSB is 0.25mV.

Range is -32mV to +31.75mV

Table 71 DC Servo Enable and Start-Up Modes

DC SERVO ACTIVE MODES

The DC Servo modes described above are suitable for initialising the DC offset correction circuit on

the Headphone outputs as part of a controlled start-up sequence which is executed before the signal

path is fully enabled. Additional modes are available for use whilst the signal path is active; these

modes may be of benefit following a large change in signal gain, which can lead to a change in DC

offset level. Periodic updates may also be desirable to remove slow drifts in DC offset caused by

changes in parameters such as device temperature.

The DC Servo circuit is enabled on HPOUT1L and HPOUT1R by setting DCS_ENA_CHAN_0 and

DCS_ENA_CHAN_1 respectively, as described earlier in Table 71.

WM8994ECS/R Datenblatt(PDF) 138 Page - Cirrus Logic

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